Integrated pixel and two-terminal non-volatile memory cell and an array of cells for deep in-sensor, in-memory computing

An integrated circuit structure comprising:

• an array of integrated pixel and two-terminal non-volatile memory cells;
• bitlines connected to columns of the cells in the array;
• and
• wordlines connected to rows of cells in the array,
• wherein each cell comprises:
• a select transistor having a gate electrically connected to a wordline for a row;
• a two-terminal non-volatile memory device;
• and
• a pixel comprising:
• a reset transistor;
• a photodiode, wherein the reset transistor is connected in series between a first voltage rail and the photodiode;
• a sense node at a junction between the reset transistor and the photodiode;
• and
• an amplifying transistor, wherein the amplifying transistor the two-terminal non-volatile memory device and the select transistor are connected in series between an adjustable second voltage rail and a bitline for a column and wherein the amplifying transistor has a gate electrically connected to the sense node.

A method comprising:

• providing an integrated circuits structure comprising:
• an array of integrated pixel and two-terminal non-volatile memory cells;
• bitlines connected to columns of the cells in the array;
• and wordlines connected to rows of cells in the array, wherein each cell comprises:
• a select transistor having a gate electrically connected to a wordline for a row;
• a two-terminal non-volatile memory device;
• and
• a pixel comprising:
• a reset transistor;
• a photodiode, wherein the reset transistor is connected in series between a first voltage rail and the photodiode;
• a sense node at a junction between the reset transistor and the photodiode;
• and
• an amplifying transistor, wherein the amplifying transistor, the two-terminal non-volatile memory device, and the select transistor are connected in series between an adjustable second voltage rail and a bitline for a column and wherein the amplifying transistor has a gate electrically connected to the sense node;
• and
• selectively operating the cells in the array in any of a write mode, a read mode, and a functional computing mode.