Neural network processor
AssigneeMicrosoft Technology Licensing, LLC
InventorsShankar S. Narayan, Ryan S. Haraden
Life of this patent
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Abstract
Each processor of the SIMD array performs the computations for a respective neuron of a neural network. As part of this computation, each processor of the SIMD array multiplies an input to a weight and accumulates the result for its assigned neuron each (MAC) instruction cycle. A table in a first memory is used to store which input is fed to each processor of the SIMD array. A crossbar is used to route a specific input to each processor each MAC cycle. A second memory is used to provide the appropriate weight to each processor that corresponds the input being routed to that processor.
Claims20
A device comprising:
- an integrated circuit including:
- an N-way single-instruction multiple data (SIMD) array of a plurality of processors including N number of processors, wherein each processor of the SIMD array includes a multiply-accumulate unit having a respective accumulator;
- and
- a crossbar to provide selected input values to the SIMD array;
- wherein the selected input values are selected from an M number of input values received at the crossbar;
- wherein the M number is greater than the N number of processors, and the M number is greater than a number of the selected input values provided to the SIMD array.
A method performed by an integrated circuit, the method comprising:
- receiving a plurality of input values at a crossbar of the integrated circuit;
- selecting, via the crossbar, a subset of the plurality of input values as selected input values, the selected input values being fewer than all of the plurality of input values;
- providing the selected input values to an N-way single-instruction multiple data (SIMD) array of a plurality of processors of the integrated circuit;
- and
- outputting a result from the SIMD array for each of the selected input values provided to the SIMD array.
An integrated circuit, comprising:
- an N-way single-instruction multiple data (SIMD) array of N number of processors, where each processor of the SIMD array includes a multiply-accumulate unit having a respective accumulator;
- and
- a crossbar to provide at least the N number of selected input values, selected from an M number of input values received at the crossbar, to the SIMD array such that each processor of the N number of processors is provided with at least a respective selected input value of the N number of selected input values;
- wherein the N number of selected input values is less than the M number of input values.
Dependencies are inferred from the claim text.