Automatic test pattern generation (atpg) for parametric faults
AssigneeSynopsys, Inc.
InventorsPeilin Jiang, Mayukh Bhattacharya, Chih Ping Antony Fan
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Abstract
Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.
Claims20
A method, comprising:
- constructing a model to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables;
- and
- determining, by a processor, a set of failure events for the IC design using the model, wherein each failure event corresponds to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.
A system, comprising:
- a memory storing instructions;
- and
- a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
- construct a model to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables;
- and
- determine a set of failure events for the IC design using the model, wherein each failure event corresponds to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.
A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
- construct a model to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables;
- and
- determine a set of failure events for the IC design using the model, wherein each failure event corresponds to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.
Dependencies are inferred from the claim text.