Memory module implementing memory centric architecture
AssigneeSunrise Memory Corporation
InventorRobert D. Norman
Life of this patent
Estimating the term…
Abstract
A semiconductor memory module for shared memory access implements memory-centric structures using a quasi-volatile memory. In one embodiment, the memory module for shared memory access includes a memory cube providing high capacity memory coupled to multiple multi-port memories to support simultaneous memory access at multiple memory interfaces. In other embodiments, a memory module incorporates a processor to implement computational memory architecture. In some embodiments, a mini core memory system implements a memory architecture for providing direct and parallel memory access to a mini processor core array.
Claims32
A memory device comprising:
- a memory module comprising one or more quasi-volatile memory circuits interconnected to at least one memory controller circuit, the memory module comprising a plurality of memory ports;
- and
- a plurality of multi-port memories coupled to the memory module at the plurality of memory ports, each multi-port memory being coupled to one memory port in the plurality of memory ports to exchange data with the memory module, each multi-port memory further comprising a plurality of memory interfaces for connecting to respective memory channels, wherein each multi-port memory comprises one or more quasi-volatile memory circuits interconnected to at least one memory controller circuit.
A memory device, comprising:
- a high density memory module comprising an array of quasi-volatile memory modules, each quasi-volatile memory module comprising one or more quasi-volatile memory circuits interconnected to at least one memory controller circuit, the high density memory module further comprising a plurality of memory ports;
- and
- a channel controller coupled to the plurality of memory ports of the high density memory module to access the array of quasi-volatile memory modules.
A mini processor core memory module, comprising:
- a first semiconductor substrate comprising a plurality of quasi-volatile memory circuits formed thereon, the plurality of quasi-volatile memory circuits being divided into memory partitions;
- and
- a second semiconductor substrate comprising a memory controller circuit to operate the quasi-volatile memory circuits as one or more quasi-volatile memories, a plurality of SRAM circuits associated with each memory partitions, and an array of mini processor cores, the second semiconductor substrate being connected to the first semiconductor substrate, wherein the array of mini processor cores accesses the memory partitions of the plurality of quasi-volatile memory circuits in parallel.
A computational memory module, comprising:
- a first semiconductor substrate comprising a plurality of quasi-volatile memory circuits formed thereon, the plurality of quasi-volatile memory circuits being divided into memory partitions;
- and
- a second semiconductor substrate comprising a memory controller circuit to operate the quasi-volatile memory circuits as one or more quasi-volatile memories, a plurality of SRAM circuits associated with each memory partitions, a processor, a code memory, and a memory access circuit, the second semiconductor substrate being connected to the first semiconductor substrate, wherein the processor accesses the memory partitions of the plurality of quasi-volatile memory circuits using the memory access circuit to exchange data in response to executing processing tasks.
A memory system for mini processor cores, comprising:
- an array of mini processor cores;
- a quasi-volatile memory module coupled to the array of mini processor cores, wherein the mini processor cores in the array directly access the quasi-volatile memory module, the quasi-volatile memory module being accessible by the array of mini processor cores in parallel;
- and
- a processor in communication with the quasi-volatile memory module to manage data movement to the array of mini processor cores.
Dependencies are inferred from the claim text.