Fpga-based acceleration using opencl on fcl in robot motion planning
AssigneeIntel Corporation
InventorsDawei Wang, Ling Liu, Xuesong Shi, Chunjie Wang, Ganmei You
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Abstract
Methods and apparatus relating to FPGA (Field-Programmable Gate Array) based acceleration in robot motion planning are described. In an embodiment, logic circuitry (such as an FPGA), coupled to a processor, accelerates one or more motion planning operations for a plurality of objects. A first memory, coupled to the logic circuitry, stores data corresponding to a plurality of Oriented Bounding Boxes (OBBs). The plurality of OBBs are to provide Bounding Volume (BV) models for the plurality of objects. Other embodiments are also disclosed and claimed.
Claims25
An apparatus comprising:
- logic circuitry, coupled to a processor, to accelerate one or more motion planning operations for a plurality of objects, wherein the one or more motion planning operations are to be initiated by the processor;
- and
- a first memory, coupled to the logic circuitry, to store data corresponding to a plurality of Oriented Bounding Boxes (OBBs), wherein the plurality of OBBs are to provide Bounding Volume (BV) models for the plurality of objects.
One or more non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:
- accelerate, at logic circuitry, one or more motion planning operations for a plurality of objects, wherein the one or more motion planning operations are to be initiated by the processor;
- and
- store data corresponding to a plurality of Oriented Bounding Boxes (OBBs) in a first memory, wherein the plurality of OBBs are to provide Bounding Volume (BV) models for the plurality of objects.
Dependencies are inferred from the claim text.