Thin-film transistor array and method of producing the same

A method of producing a thin-film transistor array, comprising:

• forming a plurality of gate electrodes and a plurality of row wirings on an insulating substrate;
• forming a gate insulating film on the insulating substrate, the gate electrodes, and the row wirings;
• forming a plurality of semiconductor patterns that overlap with the respective gate electrodes;
• forming, on the gate insulating film and the semiconductor patterns, a plurality of column wirings, a plurality of source connecting wirings, a plurality of source electrodes, a plurality of drain electrodes, a plurality of drain connecting wirings, and a plurality of drain pads;
• forming an interlayer insulating film on the column wirings, the source connecting wirings, the source electrodes, the drain electrodes, the drain connecting wirings, and the drain pads;
• forming a plurality of capacitor electrodes and a plurality of capacitor wirings on the interlayer insulating film;
• forming a capacitor insulating film on the interlayer insulating film, the capacitor electrodes, and the capacitor wirings;
• forming a plurality of drain connecting openings in the capacitor insulating film and the interlayer insulating film to be positioned over the respective drain pads;
• forming a plurality of lower pixel electrodes on the capacitor insulating film, at positions establishing connection with the respective drain pads through the drain connecting openings;
• forming an intermediate insulating film on the capacitor insulating film and the lower pixel electrodes, the intermediate insulating film having a plurality of openings in portions thereof;
• and
• forming a plurality of upper pixel electrodes on the intermediate insulating film, at positions establishing connection with the respective lower pixel electrodes through the openings.

A method of producing a thin-film transistor array, comprising:

• forming a plurality of semiconductor patterns on an insulating substrate;
• forming, on the insulating substrate and the semiconductor patterns, a plurality of column wirings, a plurality of source connecting wirings, a plurality of source electrodes, a plurality of drain electrodes, a plurality of drain connecting wirings, and a plurality of drain pads;
• forming a gate insulating film on the insulating substrate, the semiconductor patterns, the column wirings, the source connecting wirings, the source electrodes, the drain electrodes, the drain connecting wirings, and the drain pads;
• forming a plurality of gate electrodes and a plurality of row wirings on the gate insulating film;
• forming an interlayer insulating film on the gate insulating film, the gate electrodes, and the row wirings;
• forming a plurality of capacitor electrodes and a plurality of capacitor wirings on the interlayer insulating film;
• forming a capacitor insulating film on the interlayer insulating film, the capacitor electrodes, and the capacitor wirings;
• forming a plurality of drain connecting openings in the capacitor insulating film, the interlayer insulating film, and the gate insulating film to be positioned over the respective drain pads;
• forming a plurality of lower pixel electrodes on the capacitor insulating film, at positions establishing connection with the respective drain pads through the drain connecting openings;
• forming an intermediate insulating film on the capacitor insulating film and the lower pixel electrodes, the intermediate insulating film having a plurality of openings in portions thereof;
• and
• forming a plurality of upper pixel electrodes on the intermediate insulating film, at positions establishing connection with the respective lower pixel electrodes through the openings.