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US 2021/0263100 A1Published application
Multibit vectored sequential with scan
AssigneeIntel Corporation
InventorsAmit Agarwal, Ram Krishnamurthy, Satish Damaraju, Steven Hsu, Simeon Realov
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Abstract
An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.
Claims22
An apparatus comprising:
- a first scan control input;
- a second scan control input;
- a scan input;
- a first tri-stable inverter controllable by a buffered version of the first scan control input and an inverted version of the first scan control input, wherein the first tri-stable inverter is to receive the scan input;
- a second tri-stable inverter controllable by a buffered version of the second scan control input and an inverted version of the second scan control input, wherein the second tri-stable inverter is to receive an output of the first tri-stable inverter;
- a memory circuitry coupled to an output of the second tri-stable inverter;
- a third tri-stable inverter coupled to the memory circuitry and the output of the second tri-stable inverter, wherein the third tri-stable inverter is controlled by the buffered version of the first scan control input and the inverted version of the first scan control input.
4 more elements
An apparatus comprising:
- a processor circuitry;
- a memory coupled to the processor circuitry;
- a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes:
- a first circuitry including a first sequential circuitry and a second sequential circuitry;
- and
- a second circuitry to provide scan of data associated with the first circuitry, wherein the second circuitry comprises a first bit-cell and a second bit-cell, wherein a portion of the first bit-cell of the second circuitry is part of a feedback path of the first sequential circuitry, and wherein a portion of the second bit-cell of the second circuitry is part of a feedback path of the second sequential circuitry.
3 more elements
An apparatus comprising:
- a processor circuitry;
- a memory coupled to the processor circuitry;
- a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes:
- a first scan control input;
- a second scan control input;
- a scan input;
- a first tri-stable inverter controllable by a buffered version of the first scan control input and an inverted version of the first scan control input, wherein the first tri-stable inverter is to receive the scan input;
- a second tri-stable inverter controllable by a buffered version of the second scan control input and an inverted version of the second scan control input, wherein the second tri-stable inverter is to receive an output of the first tri-stable inverter;
- a memory circuitry coupled to an output of the second tri-stable inverter;
- a third tri-stable inverter coupled to the memory circuitry and the output of the second tri-stable inverter, wherein the third tri-stable inverter is controlled by the buffered version of the first scan control input and the inverted version of the first scan control input.
7 more elements
Dependencies are inferred from the claim text.