# US 2021/0243904 A1 · Direct inkjet printing of infrastructure for integrated circuits

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- Number: US 2021/0243904 A1
- Document ID: US20210243904A1
- Status: Published application
- Kind: A1
- Application number: 16/972,602
- Filed: 2019-06-04
- Published: 2021-08-05
- Earliest claimed: 2018-06-04
- Assignees: Nano Dimension Technologies, Ltd.; The IP Law Firm of Guy Levi, LLC
- Applicants: Nano-Dimension Technologies Ltd.; The IP Law Firm of Guy Levi, LLC
- Inventors: Avishai Ya'ary
- Web page: https://patentgrep.com/patent/US20210243904A1

## CPC

- H05K 3/4664: {Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders (H05K3/4647 takes precedence)}
- B41M 5/0047: {by ink-jet printing}
- G05B 19/4099: Surface or curve machining, making three-dimensional [3D] objects, e.g. desktop manufacturing
- H05K 1/162: {incorporating printed capacitors}
- H05K 3/125: {by ink-jet printing}
- H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)}
- H10W 40/10: Arrangements for heating
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04)
- B05D 1/26: performed by applying the liquid or other fluent material from an outlet device in contact with, or almost in contact with, the surface
- B05D 3/0254: {After-treatment}
- B05D 3/046: {Curing or evaporating the solvent}
- G05B 2219/45026: Circuit board, pcb
- G05B 2219/49005: Map 2-D pattern on 3-D
- H05K 1/0224: {Patterned shielding planes, ground planes or power planes (H05K1/0253 takes precedence)}
- H05K 1/095: {for polymer thick films, i.e. having a permanent organic polymeric binder}
- H05K 1/097: {Inks comprising nanoparticles and specially adapted for being sintered at low temperature (H05K1/095 takes precedence)}
- H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)}
- H05K 3/1283: {After-treatment of the printed patterns, e.g. sintering or curing methods}
- H05K 2201/0175: Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
- H05K 2201/09681: Mesh conductors, e.g. as a ground plane
- H05K 2203/013: Inkjet printing, e.g. for printing insulating material or resist
- H05K 2203/0502: Patterning and lithography
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- B41M: PRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING, (correction of typographical errors B41J; processes for applying transfer pictures or the like B44C1/16; fluid media for correction of typographical errors by coating C09D10/00; printing textiles D06P)
- G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B05D: PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL (conveying articles or workpieces through baths of liquid B65G, e.g. B65G49/02)

## Abstract

The disclosure relates to methods for direct ink jet printing of printed circuits' infrastructure. Specifically, the disclosure relates to methods for direct inkjet printing of heatdissipation elements and sockets for use in printed circuit boards (PCBs), flexible printed circuits (FPCs) and high-density interconnect (HDI) printed circuits.

## Claims

### Claim 1

An inkjet printing method for forming infrastructure element for an integrated circuit in a printed circuit board, the method comprising:
a) providing a substrate;
b) providing an ink jet printing system comprising:
i. a first print head having: at least one aperture, a dielectric ink reservoir, and a first dispenser configured to supply the dielectric ink through the aperture;
ii. a second print head having: at least one aperture, a conductive ink reservoir, and a second dispenser configured to supply the conductive ink through the aperture;
iii. a conveyor, operably coupled to the first print head and to the second print head, configured to convey the substrate to the first and second print head; and
iv. a computer aided manufacturing (“CAM”) module, comprising: a processor; a non-volatile memory; and a set of executable instructions stored on the non-volatile memory configured, when executed to cause the processor to: receive a 3D visualization file representing the infrastructure element being at least one of: a cooling pad, a heat-pipe, a condenser, a wick, a cooling platform, and a vapor chamber; using the 3D visualization file, generate a library comprising a plurality of files, each file representing a substantially 2D layer for printing of the infrastructure element; receive a selection of parameters related to the infrastructure element; and alter each of the substantially 2D layer file in the library based on at least one of the selection of parameters for printing at least one of a conducting portion and a dielectric portion of the infrastructure element;
c) providing a dielectric ink composition and a conductive ink composition;
d) using the CAM module, obtaining the generated file representing the plurality of substantially 2D layer of the infrastructure element for printing, the 2D layer comprising a pattern representative of the conductive inkjet ink and the dielectric inkjet ink, wherein the file obtained correspond to a first layer for printing;
e) using the first print head, forming the pattern corresponding to the dielectric representation in the first layer of the infrastructure element for printing;
f) curing the dielectric pattern;
g) using the second print head, forming the pattern corresponding to the conductive representation in the first layer of the infrastructure element for printing;
h) sintering the conductive pattern; and
i) repeating the steps from obtaining the generated file, wherein the file obtained correspond to a subsequent layer to a precedent layer for printing, to the step of sintering the conductive layer to the completion of the library; and wherein the printed circuit board is a multi-layered printed circuit board defining a hollow intermediate layer and wherein at least one of: the cooling pad, the heat pipe, and the wick terminates at the hollow intermediate layer.

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The method of claim 1, wherein the heat pipe is a 2-phase heat pipe

### Claim 4 (depends on 1)

The method of claim 1, wherein the infrastructure element is a socket.

### Claim 5 (depends on 4)

The method of claim 4, wherein the socket is at least partially disposed in the printed circuit board.

### Claim 6 (depends on 1)

The method of claim 1, wherein the cooling pad extends basally at an angle of less than 80° relative to the apical surface.

### Claim 7 (depends on 1)

The method of claim 1, wherein the cooling platform is in direct contact with an external heat source.

### Claim 8 (depends on 7)

The method of claim 7, wherein the external heat source is at least one of: a switch mode power integrated circuit, a dual in-line package (DIP) a Quad Flat Pack (QFP) package, a Thin Small Outline Package (TSOP), a Small Outline Integrated Circuit (SOIC) package, a Small Outline J-Lead (SOJ) package, a Plastic Leaded Chip Carrier (PLCC) package, a Wafer Level Chip Scale Package (WLCSP), a Mold Array Process-Ball Grid Array (MAPBGA) package, a Quad Flat NoLead (QFN) package, and a Land Grid Array (LGA) package, a graphic processing unit (GPU), and a central processing unit (CPU).

### Claim 9

(canceled)

### Claim 10 (depends on 1)

The method of claim 1, wherein the step of curing comprises at least one of heating, photobleaching, drying, depositing plasma, cross linking, annealing, and facilitating redox reaction.

### Claim 11 (depends on 1)

The method of claim 1, wherein sintering comprises at least one of heating and drying.

### Claim 12 (depends on 1)

The method of claim 1, wherein the parameters used in the selection of parameters related to the printed circuit board comprising the infrastructure element comprise: the type of infrastructure element, the physico-chemical characteristics of integrated circuit (IC) configured to couple to the infrastructure element, the IC packaging requirement, the heat transfer coefficient of at least the dielectric and conductive ink composition after curing and sintering respectively, or a combination of parameters comprising one or more of the foregoing.

### Claim 13

A processor readable medium storing thereon a set of executable instructions configured, when executed to cause at least one processor to:
a) receive a 3D visualization file representing the infrastructure element, wherein the infrastructure element is at least one of a cooling pad, a heat-pipe, a condenser, a wick, a cooling platform, and a vapor chamber in a multi-layered printed circuit board defining a hollow intermediate layer;
b) using the 3D visualization file, generate a library comprising a plurality of files, each file representing a substantially 2D layer for printing of the infrastructure element;
c) receive a selection of parameters related to the infrastructure element; and
d) alter each of the substantially 2D layer file in the library based on at least one of the selection of parameters for printing at least one of a conducting portion and a dielectric portion of the infrastructure element, wherein upon completion of printing of the substantially 2D layer file in the library, the at least one of: the cooling pad, the heat pipe, and the wick terminates at the hollow intermediate layer.

### Claim 14 (depends on 1)

At least one of a printed circuit board, a flexible printed circuit, a high-density interconnect circuit and their combination comprising the infrastructure element fabricated using the method of claim 1.