# US 2021/0243901 A1 · Printed circuit board and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0243901 A1 - Document ID: US20210243901A1 - Status: Published application - Kind: A1 - Application number: 17/236,519 - Filed: 2021-04-21 - Published: 2021-08-05 - Earliest claimed: 2015-07-15 - Assignees: LG Innotek Co., Ltd. - Applicants: LG Innotek Co., Ltd. - Inventors: Yun Mi BAE; Soon Gyu KWON; Sang Hwa KIM; Sang Young LEE; Jin Hak LEE; Han Su LEE; Dong Hun JEONG; In Ho JEONG; Dae Young CHOI; Jung Ho HWANG - Web page: https://patentgrep.com/patent/US20210243901A1 ## CPC - H05K 3/244: {Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465)} - C25D 3/48: of gold - C25D 5/022: {using masking means} - C25D 5/48: After-treatment of electroplated surfaces - C25D 7/123: {Semiconductors first coated with a seed layer or a conductive layer} - H05K 1/0296: {Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 (H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18)} - H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern - H05K 1/11: Printed elements for providing electric connections to or between printed circuits - H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)} - H05K 3/181: {by electroless plating (adhesives therefor H05K3/387)} - H05K 3/188: {by direct electroplating} - C25D 3/38: of copper - H05K 2201/0338: Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer - H05K 2201/098: Special shape of the cross-section of conductors, e.g. very thick plated conductors - H05K 2201/0989: Coating free areas, e.g. areas other than pads or lands free of solder resist - H05K 2201/099: Coating over pads, e.g. solder resist partly over pads - H05K 2203/1184: Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR ## Abstract A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern. ## Claims ### Claim 1 A circuit board comprising: an insulating layer; a plating seed layer disposed on the insulating layer; a circuit pattern layer disposed on the plating seed layer and formed of copper (Cu); and a protective layer disposed on the insulating layer to cover a surface of the insulating layer, wherein the circuit pattern layer includes a top surface, a bottom surface having a width greater than a width of the top surface, and a side surface connecting the top surface and the bottom surface, and wherein the side surface of the circuit pattern layer has a curved surface connected to the top surface. ### Claim 2 (depends on 1) The circuit board of claim 1, wherein the curved surface of the circuit pattern layer is not connected to the bottom surface of the circuit pattern layer. ### Claim 3 (depends on 1) The circuit board of claim 1, wherein a level of a top surface of the protective layer is higher than a level of the top surface of the circuit pattern layer. ### Claim 4 (depends on 1) The circuit board of claim 1, wherein the protective layer covers at least a portion of the top surface of the circuit pattern layer, at least a portion of a left lateral area of the circuit pattern layer, at least a portion of a right lateral area of the circuit pattern layer, or a combination thereof. ### Claim 5 (depends on 1) The circuit board of claim 1, comprising: a surface treatment layer disposed on the circuit pattern layer and formed of gold (Au); and wherein the protective layer has an opening to expose a top surface of the surface treatment layer. ### Claim 6 (depends on 1) The circuit board of claim 1, wherein the protective layer includes a solder resist. ### Claim 7 (depends on 1) The circuit board of claim 1, wherein the side surface of the circuit pattern layer comprises: a first portion connected with the top surface of the circuit pattern layer and corresponding to the curved surface, and a second portion connecting between the first portion and the bottom surface of the circuit pattern layer and other than the curved surface. ### Claim 8 (depends on 5) The circuit board of claim 5, wherein a bottom surface of the surface treatment layer comprises: a first bottom surface contacted with the top surface of circuit pattern layer, and a second bottom surface spaced apart from the top surface of the circuit pattern layer. ### Claim 9 (depends on 8) The circuit board of claim 8, wherein the protective layer contacts the curved surface of the circuit pattern layer and the second bottom surface of the surface treatment layer. ### Claim 10 (depends on 1) The circuit board of claim 1, wherein the protective layer exposes a portion of the surface of the insulating layer. ### Claim 11 (depends on 9) The circuit board of claim 9, wherein the protective layer is spaced apart from the circuit pattern layer, the plating seed layer, and the surface treatment layer. ### Claim 12 A circuit board comprising: an insulating layer; a plating seed layer disposed on the insulating layer; a circuit pattern layer disposed on the plating seed layer and formed of copper (Cu); a surface treatment layer disposed on the circuit pattern layer and formed of gold (Au); and a protective layer disposed on the insulating layer to cover a surface of the insulating layer, wherein a width of a top surface of the circuit pattern layer is narrower than a width of a bottom surface of the circuit pattern layer, wherein the circuit pattern layer includes a top surface, a bottom surface having a width greater than a width of the top surface, and a side surface connecting the top surface and the bottom surface, wherein the side surface of the circuit pattern layer has a curved surface spaced apart from the bottom surface of circuit pattern layer. ### Claim 13 (depends on 12) The circuit board of claim 12, wherein a bottom surface of the surface treatment layer comprises: a first bottom surface contacted with the top surface of the circuit pattern layer; and a second bottom surface spaced apart from the top surface of the circuit pattern layer, and wherein a level of a top surface of the protective layer is different from a level of the top surface of the circuit pattern layer. ### Claim 14 (depends on 13) The circuit board of claim 13, wherein the level of the top surface of the protective layer is higher than the level of the top surface of the circuit pattern layer. ### Claim 15 (depends on 13) The circuit board of claim 13, wherein the protective layer covers a left lateral side of the circuit pattern layer, a right lateral side of the circuit pattern layer, a lateral side of the plating layer, a portion of the top surface of the surface treatment layer, or a combination thereof. ### Claim 16 (depends on 13) The circuit board of claim 13, wherein the protective layer includes a solder resist. ### Claim 17 (depends on 13) The board of claim 13, wherein the circuit pattern layer comprises: a first portion contacted with a top surface of the plating seed layer; and a second portion contacted with a top surface of the first portion and the bottom surface of the surface treatment layer, wherein the second portion of the circuit pattern layer is formed such that top and bottom surfaces thereof have widths different from each other, wherein the first bottom surface of the surface treatment layer is contacted with the second portion of the circuit pattern layer, and wherein the second bottom surface of the surface treatment layer is spaced apart from the top surface of the second portion of the circuit pattern layer. ### Claim 18 (depends on 17) The board of claim 17, wherein the first portion of the circuit pattern layer comprises: a first area overlapped with the surface treatment layer in a vertical direction; and a second area not overlapped with the surface treatment layer in the vertical direction. ### Claim 19 (depends on 17) The circuit board of claim 17, wherein the first bottom surface of the surface treatment layer including gold (Au) is in direct physical contact with the top surface of the circuit pattern layer including copper (Cu).