# US 2021/0243729 A1 · Methods and apparatus for descrambling received uplink transmissions

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- Number: US 2021/0243729 A1
- Document ID: US20210243729A1
- Status: Published application
- Kind: A1
- Application number: 17/239,272
- Filed: 2021-04-23
- Published: 2021-08-05
- Earliest claimed: 2018-05-31
- Assignees: Marvell Asia Pte Ltd
- Applicants: Marvell Asia Pte, Ltd.
- Inventors: Sabih Guzelgoz; Hong Jik Kim
- Web page: https://patentgrep.com/patent/US20210243729A1

## CPC

- H04L 1/0073: {Special arrangements for feedback channel}
- H04W 72/04: Wireless resource allocation
- H04L 1/0045: {Arrangements at the receiver end}
- H04L 5/0053: {Allocation of signalling, i.e. of overhead other than pilot signals}
- H04L 1/1664: {the supervisory signal being transmitted together with payload signals; piggybacking}
- H04L 1/1671: {the supervisory signal being transmitted together with control information}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)

## Abstract

Methods and apparatus for providing a resource element identification system to process received uplink transmissions. In an embodiment, a method is provided that includes receiving soft-demapped symbols that comprises resource elements. The method also includes descrambling the resource elements of the symbols one-by-one using descrambling bits generated by at least one linear feedback shift register (LFSR). After each symbol is descrambled, a state of the at least one LFSR is stored as a stored state. The method also comprises restoring the stored state to the at least one LFSR before a next symbol is descrambled so that generation of the descrambling bits continues from symbol to symbol. The method also comprises forwarding the descrambled symbols to a downstream combining function.

## Claims

### Claim 1

An apparatus for facilitating network communication, comprising:
a configuration parameters block configured to provide a plurality of configuration parameters wherein a first set of parameters is configured for managing gain normalization, a second set of parameters is configured for despreading operation, and a third set of parameters is configured for descrambling operation;
a gain normalizer coupled to the configuration parameters block and configured to perform a gain normalization function on the received uplink transmission in accordance with the first set of parameters; and
a descrambler coupled to the configuration parameters block and configured to descramble received resource elements (“REs”) in response to the third set of parameters.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a despreader coupled to the configuration parameters block and configured to spreading sequence index and spreading type in accordance with the third set of parameters.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a receiver that receives soft-demapped symbols, wherein each symbol comprises resource elements.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the descrambler is configured to descramble the REs of symbols one-by-one using descrambling bits generated by at least one linear feedback shift register (“LFSR”).

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein a state of the at least one LFSR is stored as a stored state in a memory after each symbol is descrambled.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the descrambler retrieves the stored state from the memory and restores the stored state to the at least one LFSR before a plurality of resource elements of a next symbol is descrambled.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising an output interface configured to forward descrambled symbols to a downstream combining function.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising a combiner coupled to the descrambler and configured to combine descrambled resource elements that are identified to contain acknowledgement information to produce combined acknowledgement information.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the combiner is configured to store the combined acknowledgement information in a memory.

### Claim 10 (depends on 1)

The apparatus of claim 1, further comprising a combiner coupled to the descrambler and operable to combine descrambled resource elements that are identified to contain channel state information to produce combined channel state information and store the combined channel state information in a memory.

### Claim 11

A method for facilitating network communication, comprising:
receiving resource elements (“REs”) of a first symbol from a soft demapper;
retrieving at least a portion of output bits from at least one shift register;
descrambling the REs of the first symbol to generate descrambled REs of the first symbol in accordance with the portion of output bits and configuration parameters;
storing the descrambled REs of the first symbol in an internal memory; and
storing state of the at least one shifter register in an external memory for next descrambling of REs of a second symbol.

### Claim 12 (depends on 11)

The method of claim 11, further comprising restoring state of at least one linear feedback shift register (“LFSR”) in accordance with previous state of the LFSR stored in the external memory before descrambling REs from the second symbol.

### Claim 13 (depends on 12)

The method of claim 12, further comprising allowing subsequent operation of the LFSR continued from previous descrambling of the first symbol.

### Claim 14 (depends on 12)

The method of claim 12, further comprising descrambling REs for the second symbol in response to the LFSR until the REs of the next symbol exhausted.

### Claim 15 (depends on 14)

The method of claim 14, further comprising storing current state of the LFSR in the external memory.

### Claim 16 (depends on 11)

The method of claim 11, further comprising forwarding the descrambled REs of the first symbols to a downstream combining function.

### Claim 17

An apparatus for facilitating wireless network communication, comprising:
means for receiving resource elements (“REs”) of a first symbol from a soft demapper;
means for retrieving at least a portion of output bits from at least one shift register;
means for descrambling the REs of the first symbol to generate descrambled REs of the first symbol in accordance with the portion of output bits and configuration parameters;
means for storing the descrambled REs of the first symbol in an internal memory; and
means for storing state of the at least one shifter register in an external memory for next descrambling of REs of a second symbol.

### Claim 18 (depends on 17)

The apparatus of claim 17, further comprising means for restoring state of at least one linear feedback shift register (“LFSR”) in accordance with previous state of the LFSR stored in the external memory before descrambling REs from the second symbol.

### Claim 19 (depends on 18)

The apparatus of claim 18, further comprising means for allowing subsequent operation of the LFSR continued from previous descrambling of the first symbol.

### Claim 20 (depends on 18)

The apparatus of claim 18, further comprising means for descrambling REs for the second symbol in response to the LFSR until the REs of the next symbol exhausted.

### Claim 21 (depends on 18)

The apparatus of claim 18, further comprising means for storing current state of the LFSR in the external memory.

### Claim 22 (depends on 17)

The method of claim 17, further comprising means for forwarding the descrambled REs of the first symbols to a downstream combining function.

### Claim 23

A network processing device for facilitating network communication, comprising:
an internal memory able to store processed resource elements (“REs”) of at least one symbol;
a set of linear feedback shift registers (“LFSRs”) coupled to the internal memory and operable to store information relating to a descrambling sequence; and
a descrambling processor, coupled to the set of LFSRs, configured to receiving soft-demapped symbols and configuration parameters, the descrambling processor operable to descramble the REs with a sequence of symbol by symbol in response to descrambling bits generated by at least one LFSR and configuration parameters, the descrambling processor configured to store descrambled REs in the internal memory and store a state of a state of the at least one LFSR in an external memory.

### Claim 24 (depends on 23)

The device of claim 23, further comprising an output interface coupled to the descrambling processor and configured to output the descrambled REs to a combiner.

### Claim 25 (depends on 23)

The device of claim 23, wherein the descrambling processor includes a sequence modifier operable to modify descrambling sequences for certain categories of uplink control information (“UCI”).

### Claim 26 (depends on 23)

The device of claim 23, wherein the descrambling processor is capable of retrieving stored state from an external memory and restoring the stored state to the at least one LFSR before processing next symbol.

### Claim 27 (depends on 23)

The device of claim 23, further comprising a combiner coupled to the descrambling processor and configured to combine descrambled REs that are identified to contain acknowledgement information to produce combined acknowledgement information.

### Claim 28 (depends on 27)

The device of claim 27, wherein the combiner is configured to store the combined acknowledgement information in a memory.

### Claim 29 (depends on 23)

The device of claim 23, further comprising a combiner coupled to the descrambling processor and operable to combine descrambled REs that are identified to contain channel state information to produce combined channel state information.

### Claim 30 (depends on 29)

The device of claim 29, wherein the combiner stores the combined the channel state information in a memory.

### Claim 31 (depends on 23)

The device of claim 23, further comprising a configuration parameters block coupled to the descrambling processor and configured to provide a plurality of configuration parameters wherein a first set of parameters is configured for managing gain normalization and a second set of parameters is configured for despreading operation.

### Claim 32 (depends on 23)

The device of claim 23, further comprising a despreader coupled to the descrambling processor and configured to spreading sequence index and spreading type in accordance with the third set of parameters.