# US 2021/0243397 A1 · Image sensors with variable read out circuitry

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- Number: US 2021/0243397 A1
- Document ID: US20210243397A1
- Status: Published application
- Kind: A1
- Application number: 16/949,540
- Filed: 2020-11-03
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Nicholas Paul COWLEY; Andrew David TALBOT; Mukesh Rao ENGLA SYAM
- Web page: https://patentgrep.com/patent/US20210243397A1

## CPC

- H04N 25/771: comprising storage means other than floating diffusion
- H04N 25/00: Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N 25/41: {Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors}
- H04N 25/767: Horizontal readout lines, multiplexers or registers
- H04N 25/7795: {Circuitry for generating timing or clock signals}
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

An imaging device may have an array of image sensor pixels arranged in rows and columns and column readout circuitry coupled to the array. The rows of pixels may receive drive signals from row driver circuitry, and the drive signals may be sent from timing circuitry based on the locations of rows within the array. In particular, rows closer to the readout circuitry may require less settling time and therefore be driven faster than the rows further from the readout circuitry. All of the rows may be driven in a single direction, or the array of pixels may have a cut, in which case rows above the cut may be driven up and rows below the cut may be driven down. A frame buffer may be used to store the signals generated by the rows of pixels and may account for the asynchronous read out of image data.

## Claims

### Claim 1

An imaging system comprising:
an array of pixels arranged in rows and columns and configured to generate image signals in response to incident light;
variable timing circuitry that is configured to drive inputs to the rows of pixels in the array of pixels at variable rates; and
column output circuitry configured to output the image signals generated by the pixels in the rows of pixels in response to the inputs.

### Claim 2 (depends on 1)

The imaging system defined in claim 1 wherein the variable timing circuitry is configured to select the variable rate for a given row based on the distance of the given row from the column output circuitry.

### Claim 3 (depends on 2)

The imaging system defined in claim 2 wherein the variable timing circuitry is configured to output unique rates to at least two groups of rows of the array of pixels.

### Claim 4 (depends on 3)

The imaging system defined in claim 3 wherein a first group of rows of the at least two groups of rows is a first distance from the column output circuitry, wherein a second group of rows of the at least two groups of rows is a second distance from the column output circuitry, wherein the second distance is greater than the first distance, and wherein the first group of rows is configured to be read out at a faster rate than the second group of rows.

### Claim 5 (depends on 4)

The imaging system defined in claim 4 wherein the column output circuitry is located at an upper end of the array of pixels, wherein the first group of rows comprises an uppermost row of the array, and wherein the second group of pixels comprises a lowermost row of the array.

### Claim 6 (depends on 4)

The imaging system defined in claim 4 wherein the column output circuitry is located at a lower end of the array of pixels, wherein the first group of rows comprises a lowermost row of the array, and wherein the second group of pixels comprises an uppermost row of the array.

### Claim 7 (depends on 3)

The imaging system defined in claim 3 wherein the column output circuitry is first column output circuitry located at an upper end of the array of pixels, the image sensor further comprising:
second column output circuitry located at a lower end of the array of pixels.

### Claim 8 (depends on 7)

The imaging system defined in claim 7 wherein the array of pixels comprises a cut, wherein image pixels above the cut are configured to be read out through the first column output circuitry and wherein image pixels below the cut are configured to be read out through the second column output circuitry.

### Claim 9 (depends on 8)

The imaging system defined in claim 8 wherein an uppermost row of pixels of the array and a lowermost row of pixels of the array are configured to be read out simultaneously, and wherein rows adjacent to the cut on top and bottom halves of the array are configured to be read out simultaneously.

### Claim 10 (depends on 8)

The imaging system defined in claim 8 wherein an uppermost row of pixels of the array and a row adjacent to the cut on a bottom half of the array are configured to be driven to be read out at the same time, and wherein a lowermost row of pixels of the array is configured to be driven to be read out while a row adjacent to the cut on a top half of the array is being read out.

### Claim 11 (depends on 1)

The imaging system defined in claim 1 further comprising:
a frame buffer configured to store the outputs of the rows of pixels; and
a data interface interposed between the frame buffer and the column output circuitry.

### Claim 12 (depends on 11)

The imaging system defined in claim 11 wherein the frame buffer is a collocated frame buffer.

### Claim 13 (depends on 11)

The imaging system defined in claim 11 wherein the frame buffer is a non-collocated frame buffer and wherein at least some of the outputs of the rows of pixels are configured to be passed through the data interface using a full bandwidth of the data interface.

### Claim 14

A method comprising:
generating image signals using an image pixel array comprising rows and columns of image pixels;
with row driver circuitry, generating readout signals with variable timing based on positions of the rows in the array;
reading out the image signals of the rows of pixels over column readout circuitry; and
storing the image signals in a frame buffer.

### Claim 15 (depends on 14)

The method defined in claim 14 further comprising:
after reading out the image signals of the rows of pixels over the column readout circuitry, reading out the image signals through a data interface.

### Claim 16 (depends on 14)

The method defined in claim 14 wherein generating the readout signals with variable timing comprises generating the readout signals with unique timings for at least two groups of rows in the array.

### Claim 17 (depends on 16)

The method defined in claim 16 wherein reading out the image signals comprises reading all of the rows in an upwards or a downwards direction.

### Claim 18 (depends on 16)

The method defined in claim 16 wherein reading out the image signals comprises reading rows above a cut toward first column circuitry at an upper portion of the array and reading out rows below the cut toward second column circuitry at a lower portion of the array.

### Claim 19

An imaging system comprising:
an image sensor comprising:
an image pixel array comprising rows and columns of image pixels that are configured to generate image signals;
column output circuitry configured to output the image signals generated by the pixels in the rows of pixels;
row driver circuitry that is configured to drive the image signals from the rows to the column output circuitry;
variable timing circuitry configured to drive the row driver circuitry at a variable rate that is determined based on a location of a given row in the array; and
a data interface that receives the image signals from the column readout circuitry; and
an image processor comprising:
a frame buffer configured to store the image signals as they are read out.

### Claim 20 (depends on 19)

The image sensor defined in claim 19 wherein the variable timing circuitry is configured to drive the row driver circuitry with unique rates for at least three different groups of rows in the array.