# US 2021/0243393 A1 · Solid-state imaging element and imaging device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0243393 A1 - Document ID: US20210243393A1 - Status: Published application - Kind: A1 - Application number: 17/042,087 - Filed: 2019-01-10 - Published: 2021-08-05 - Earliest claimed: 2018-04-04 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: KAZUYA YONEMOTO - Web page: https://patentgrep.com/patent/US20210243393A1 ## CPC - H04N 25/59: by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance - H04N 25/63: applied to dark current - H04N 25/771: comprising storage means other than floating diffusion - H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H10F 39/12: Image sensors - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract To improve the conversion efficiency of converting charge to voltage in a solid-state imaging element that stores charge in a charge storage unit. A high-sensitivity-side transfer transistor is configured to transfer a charge from a high-sensitivity photodiode having a sensitivity higher than a predetermined sensitivity to a first charge storage unit. A low-sensitivity-side transfer transistor is configured to transfer a charge from a low-sensitivity photodiode having a sensitivity lower than the predetermined sensitivity to a second charge storage unit. An amplification transistor is configured to amplify a voltage of the first charge storage unit. A first conversion efficiency control transistor is configured to control a conversion efficiency of converting the charge to the voltage by opening and closing a pathway between the first and second charge storage units. A second conversion efficiency control transistor is configured to control the conversion efficiency by opening and closing a pathway between the second charge storage unit and a third charge storage unit. ## Claims ### Claim 1 A solid-state imaging element comprising: a high-sensitivity-side transfer transistor configured to transfer a charge from a high-sensitivity photodiode having a sensitivity higher than a predetermined sensitivity to a first charge storage unit; a low-sensitivity-side transfer transistor configured to transfer a charge from a low-sensitivity photodiode having a sensitivity lower than the predetermined sensitivity to a second charge storage unit; an amplification transistor configured to amplify a voltage of the first charge storage unit; a first conversion efficiency control transistor configured to control a conversion efficiency of converting the charge to the voltage by opening and closing a pathway between the first and second charge storage units; and a second conversion efficiency control transistor configured to control the conversion efficiency by opening and closing a pathway between the second charge storage unit and a third charge storage unit. ### Claim 2 (depends on 1) The solid-state imaging element according to claim 1, further comprising: a select transistor configured to output a signal of the amplified voltage; and a driving circuit configured to drive each of the high-sensitivity-side transfer transistor, the low-sensitivity-side transfer transistor, the first and second conversion efficiency control transistors, and the select transistor. ### Claim 3 (depends on 2) The solid-state imaging element according to claim 2, wherein the driving circuit causes the high-sensitivity-side transfer transistor to transfer the charge inside a period in which both the first and second conversion efficiency control transistors are switched off and also causes the select transistor to output a signal of the voltage as a first voltage signal. ### Claim 4 (depends on 2) The solid-state imaging element according to claim 2, wherein the driving circuit causes the high-sensitivity-side transfer transistor to transfer the charge inside a period in which the first conversion efficiency control transistor is switched on and the second conversion efficiency control transistor is switched off and also causes the select transistor to output a signal of the voltage as a second voltage signal. ### Claim 5 (depends on 2) The solid-state imaging element according to claim 2, wherein the driving circuit causes the low-sensitivity-side transfer transistor to transfer the charge inside a period in which the first conversion efficiency control transistor is switched on and the second conversion efficiency control transistor is switched off and also causes the select transistor to output a signal of the voltage as a third voltage signal. ### Claim 6 (depends on 5) The solid-state imaging element according to claim 5, wherein the driving circuit causes the select transistor to output a signal of the voltage according to a charge overflowing from the high-sensitivity photodiode inside a period in which both the first and second conversion efficiency control transistors are switched on as a fourth voltage signal. ### Claim 7 (depends on 6) The solid-state imaging element according to claim 6, wherein the driving circuit causes the fourth voltage signal to be output before causing the third voltage signal to be output. ### Claim 8 (depends on 6) The solid-state imaging element according to claim 6, wherein the driving circuit supplies, to the low-sensitivity-side transfer transistor, a readout pulse of middle potential between a predetermined potential and a high potential higher than the predetermined potential before causing the third and fourth voltage signals to be output. ### Claim 9 (depends on 6) The solid-state imaging element according to claim 6, further comprising: a signal amount correction processing unit configured to execute a process of combining the third voltage signal and the fourth voltage signal as a signal amount correction process. ### Claim 10 (depends on 9) The solid-state imaging element according to claim 9, further comprising: a determination unit configured to determine whether or not an amount of light is less than a predetermined value on a basis of the first, second, and third voltage signals; an arithmetic mean processing unit configured to compute an arithmetic mean value of each of the fourth voltage signals output when the amount of light is less than the predetermined value; and a dark current correction processing unit configured to subtract a dark current according to the arithmetic mean value from the fourth voltage signal, and supply the subtracted result to the signal amount correction processing unit. ### Claim 11 (depends on 1) The solid-state imaging element according to claim 1, wherein the third charge storage unit is a capacitance of a metal-oxide-semiconductor (MOS) transistor having a gate connected to the second conversion efficiency control transistor and a source into which a predetermined source bias pulse is input, and the driving circuit supplies the source bias pulse higher than a predetermined potential outside a predetermined exposure period, and supplies the source bias pulse lower than the predetermined potential outside the predetermined exposure period. ### Claim 12 (depends on 11) The solid-state imaging element according to claim 11, wherein the gate of the MOS transistor is embedded in a first trench formed in a predetermined substrate. ### Claim 13 (depends on 12) The solid-state imaging element according to claim 12, wherein in the predetermined substrate, the MOS transistor and at least one of the high-sensitivity photodiode or the low-sensitivity photodiode are isolated from each other by a second trench. ### Claim 14 (depends on 1) The solid-state imaging element according to claim 1, wherein the high-sensitivity-side transfer transistor, the low-sensitivity-side transfer transistor, and the first and second conversion efficiency control transistors are each respectively disposed in each of a plurality of pixel circuits arrayed in a two-dimensional matrix, and one of a pair of pixel circuits adjacent in a predetermined direction among the plurality of pixel circuits is connected to a first signal line, while the other of the pair is connected to a second signal line. ### Claim 15 (depends on 14) The solid-state imaging element according to claim 14, further comprising: a first analog-to-digital converter configured to convert a first analog signal to a digital signal; a second analog-to-digital converter configured to convert a second analog signal to a digital signal; a first switch configured to treat a signal from one of the first and second signal lines as the first analog signal and output the first analog signal to the first analog-to-digital converter; and a second switch configured to treat a signal from the other of the first and second signal lines as the second analog signal and output the second analog signal to the second analog-to-digital converter. ### Claim 16 An imaging device comprising: a high-sensitivity-side transfer transistor configured to transfer a charge from a high-sensitivity photodiode having a sensitivity higher than a predetermined sensitivity to a first charge storage unit; a low-sensitivity-side transfer transistor configured to transfer a charge from a low-sensitivity photodiode having a sensitivity lower than the predetermined sensitivity to a second charge storage unit; an amplification transistor configured to amplify a voltage of the first charge storage unit; a first conversion efficiency control transistor configured to control a conversion efficiency of converting the charge to the voltage by opening and closing a pathway between the first and second charge storage units; a second conversion efficiency control transistor configured to control the conversion efficiency by opening and closing a pathway between the second charge storage unit and a third charge storage unit; and a signal processing unit configured to perform predetermined signal processing on a signal of the amplified voltage.