# US 2021/0243041 A1 · System and method for performing netlist obfuscation for a semiconductor device

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- Number: US 2021/0243041 A1
- Document ID: US20210243041A1
- Status: Published application
- Kind: A1
- Application number: 16/778,442
- Filed: 2020-01-31
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: NXP B.V.
- Applicants: NXP B.V.
- Inventors: Jan-Peter SCHAT
- Web page: https://patentgrep.com/patent/US20210243041A1

## CPC

- H04L 9/3278: {using physically unclonable functions [PUF]}
- G06F 21/6254: {by anonymising data, e.g. decorrelating personal data from the owner's identification}
- G06F 21/74: operating in dual or compartmented mode, i.e. at least one secure mode
- H03K 3/037: Bistable circuits
- H03K 19/003: Modifications for increasing the reliability {for protection}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A tie cell includes a first flip-flop having a physically unclonable function (PUF), a second flip-flop that generates a PUF key value, and logic that logically combines the PUF value and the PUF key value to generate an output signal having a constant logical value. The PUF value is based on a power-up value stored in the first flip-flop, which power-up value is generated based on physical and/or electrical characteristics produced from a manufacturing process. The output value is generated to tie digital logic to the constant logical value.

## Claims

### Claim 1

A tie cell, comprising:
a first flip-flop including a physically unclonable function (PUF);
a second flip-flop configured to generate a PUF key value; and
logic configured to combine a value of the PUF and the PUF key value to generate an output signal having a constant logical value, wherein the PUF value is based on a power-up value stored in the first flip-flop, the power-up value generated as a result of physical and/or electrical characteristics produced from a manufacturing process, and wherein the output value is generated to tie digital logic to the constant logical value.

### Claim 2 (depends on 1)

The tie cell of claim 1, further comprising:
a selector coupled to an input of the second flip-flop,
wherein the selector is configured to select:
in a first mode, a first signal based on the PUF value output from the first flip-flop, and
in a second mode, a second signal based on the PUF key value.

### Claim 3 (depends on 2)

The tie cell of claim 2, wherein:
the first mode is a scan test capture mode to provide notification of the PUF value; and
the second mode is a scan test mode to determine existence of a fault in the tie cell.

### Claim 4 (depends on 3)

The tie cell of claim 3, wherein the second flip-flop is to store the PUF value in the scan test capture mode.

### Claim 5 (depends on 3)

The tie cell of claim 3, wherein the second flip-flop is to store and then shift the PUF key value to the logic in the scan test mode.

### Claim 6 (depends on 1)

The tie cell of claim 1, wherein the logic includes XOR logic.

### Claim 7 (depends on 6)

The tie cell of claim 6, wherein the PUF key value is:
equal to the PUF value when the constant logical value is zero, and
different from the PUF value when the constant logical value is one.

### Claim 8

An integrated circuit, comprising:
a first tie cell configured to generate a first signal;
a second tie cell configured to generate a second signal; and
a controller configured to generate at least one control signal for one or both of the first tie cell and the second tie cell, wherein the first tie cell embodies a first physically unclonable function (PUF) and the second tie cell includes a second PUF different from the first PUF and wherein the first signal has a constant first logical value and the second signal has a constant second logical value different from the first logical value.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the controller is configured to generate the at least one control signal to activate the first tie cell during a time when the second tie cell is inactive.

### Claim 10 (depends on 8)

The integrated circuit of claim 8, wherein the first tie cell includes:
a first flip-flop including the first PUF;
a second flip-flop configured to generate a PUF key value; and
logic configured to combine a value of the PUF and the PUF key value to generate an output signal having a constant logical value, wherein the PUF value is based on a power-up value stored in the first flip-flop, the power-up value generated as a result of physical and/or electrical characteristics produced from a manufacturing process, and wherein the output value is generated to tie digital logic to the constant logical value.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, further comprising:
a selector coupled to an input of the second flip-flop,
wherein the selector is configured to select
in a first mode, a first signal based on the PUF value output from the first flip-flop, and
in a second mode, a second signal based on the PUF key value.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein:
the first mode is a scan test capture mode to provide notification of the PUF value; and
the second mode is a scan test mode to determine existence of a fault in the tie cell.

### Claim 13 (depends on 12)

The integrated circuit of claim 12, wherein the second flip-flop is to store the PUF value in the scan test capture mode.

### Claim 14 (depends on 12)

The integrated circuit of claim 12, wherein the second flip-flop is to store and then shift the PUF key value to the logic in the scan test mode.

### Claim 15 (depends on 10)

The integrated circuit of claim 10, wherein the logic includes XOR logic.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein the PUF key value is:
equal to the PUF value when the constant logical value is zero, and
different from the PUF value when the constant logical value is one.

### Claim 17

A method for controlling an integrated circuit, comprising:
obtaining a value correspond to a physically unclonable function (PUF);
generating a PUF key value based on the PUF value; and
logically combining the PUF value and the PUF key value to generate an output signal having a constant logical value, wherein the PUF value is based on a power-up value stored in a first flip-flop in a tie cell, the power-up value generated as a result of physical and/or electrical characteristics produced from a manufacturing process, and wherein the output value is generated to tie digital logic to the constant logical value.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
selecting a signal for input into a second flip-flop in the tie cell,
wherein the signal is based on the PUF value output from the first flop-flop in a first mode and the signal is based on the PUF key value in a second mode.

### Claim 19 (depends on 17)

The method of claim 17, wherein the PUF value and the PUF key value are logically combined by XOR logic.

### Claim 20 (depends on 19)

The method of claim 19, wherein the PUF key value is
equal to the PUF value when the constant logical value is zero, and
different from the PUF value when the constant logical value is one.