# US 2021/0242878 A1 · Compensation circuit for delta-sigma modulators, corresponding device and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242878 A1 - Document ID: US20210242878A1 - Status: Published application - Kind: A1 - Application number: 17/163,230 - Filed: 2021-01-29 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: STMicroelectronics S.r.l. - Applicants: STMICROELECTRONICS S.r.l. - Inventors: Roberto MODAFFARI; Paolo PESENTI; Germano NICOLLINI - Web page: https://patentgrep.com/patent/US20210242878A1 ## CPC - H03M 3/37: {Compensation or reduction of delay or phase error} - H03M 3/02: Delta modulation, i.e. one-bit differential modulation {(H03M3/30 takes precedence)} - H03M 3/452: {with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input} - H03M 3/464: {Details of the digital/analogue conversion in the feedback path} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal. ## Claims ### Claim at position 1 -34. (canceled) ### Claim 35 A system, comprising: an input interface, which, in operation, receives an analog input signal; an output interface, which, in operation, outputs a delta-sigma modulated signal; and a delta-sigma modulation circuit having a sampling period and coupled between the input interface and the output interface, wherein the delta-sigma modulation circuit, in operation, generates the delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including: a first integrator; an analog-to-digital converter coupled to the output interface; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter; and loop-delay compensation circuitry having a plurality of switches, wherein the loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal, wherein the loop-delay compensation circuitry includes a derivative circuit coupled between an output of the first integrator and the plurality of switches; the feedback-loop includes: a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator; and a first digital-to-analog converter coupled between the output interface and a second input of the first adder; and the delta-sigma modulation circuit includes: a second adder having a first input coupled to an output of the first integrator, a second input coupled to an output of the loop-delay compensation circuitry, and an output coupled to the second integrator; and a third adder having a first input coupled to an output of the first integrator, a second input coupled to an output of the second integrator and an output coupled to the analog-to-digital converter. ### Claim 36 (depends on 35) The system of claim 35 wherein, the first digital-to-analog converter, in operation, generates a first weighted feedback signal. ### Claim 37 (depends on 35) The system of claim 35 wherein the delta-sigma modulation circuit comprises an inverter coupled between the output of the first integrator and the first input of the third adder. ### Claim 38 A system, comprising: an input interface, which, in operation, receives an analog input signal; an output interface, which, in operation, outputs a delta-sigma modulated signal; and a delta-sigma modulation circuit having a sampling period and coupled between the input interface and the output interface, wherein the delta-sigma modulation circuit, in operation, generates the delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including: a first integrator; an analog-to-digital converter coupled to the output interface; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter; and loop-delay compensation circuitry having a plurality of switches, wherein the loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal, wherein the loop-delay compensation circuitry includes a derivative circuit coupled between an output of the first integrator and the plurality of switches; and the loop-delay compensation circuitry comprises a third integrator coupled to an output of the plurality of switches. ### Claim 39 (depends on 38) The system of claim 38 wherein, the feedback-loop includes: a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator; a first digital-to-analog converter coupled between the output interface and a second input of the first adder; a second adder having a first input coupled to an output of the first integrator and an output coupled to an input of the second integrator; and a second digital-to-analog converter coupled between the output interface and a second input of the second adder; and the loop-delay compensation circuitry comprises a third adder having a first input coupled to an output of the second integrator, a second input coupled to an output of the third integrator and an output coupled to the analog-to-digital converter. ### Claim 40 (depends on 39) The system of claim 39 wherein, the first digital-to-analog converter, in operation, generates a first weighted feedback signal; and the second digital-to-analog converter, in operation, generates a second weighted feedback signal. ### Claim 41 (depends on 38) The system of claim 38 wherein, the feedback-loop includes: a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator; and a first digital-to-analog converter coupled between the output interface and a second input of the first adder; and the loop-delay compensation circuitry comprises a second adder having a first input coupled to an output of the second integrator, a second input coupled to an output of the third integrator and an output coupled to the analog-to-digital converter. ### Claim 42 (depends on 41) The system of claim 41 wherein, the first digital-to-analog converter, in operation, generates a first weighted feedback signal. ### Claim 43 (depends on 41) The system of claim 41 wherein, the delta-sigma modulation circuit includes a third adder coupled between the output of the second integrator and the second adder, the third adder having a first input coupled to an output of the first integrator, a second input coupled to the output of the second integrator and an output coupled to the first input of the second adder. ### Claim 44 (depends on 43) The system of claim 43 wherein the delta-sigma modulation circuit comprises an inverter coupled between the output of the first integrator and the first input of the third adder. ### Claim 45 (depends on 38) The system of claim 38 wherein, the feedback-loop includes: a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator; a first digital-to-analog converter coupled between the output interface and a second input of the first adder; a second adder having a first input coupled to an output of the first integrator and an output coupled to an input of the second integrator; and a second digital-to-analog converter coupled between the output interface and a second input of the second adder; and an output of the loop-delay compensation circuitry is coupled to a third input of the second adder. ### Claim 46 (depends on 45) The system of claim 45 wherein, the first digital-to-analog converter, in operation, generates a first weighted feedback signal; and the second digital-to-analog converter, in operation, generates a second weighted feedback signal. ### Claim 47 A system, comprising: an input interface, which, in operation, receives an analog input signal; an output interface, which, in operation, outputs a delta-sigma modulated signal; and a delta-sigma modulation circuit having a sampling period and coupled between the input interface and the output interface, wherein the delta-sigma modulation circuit, in operation, generates the delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including: a first integrator; an analog-to-digital converter coupled to the output interface; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter; and loop-delay compensation circuitry having a plurality of switches, wherein the loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal, wherein the first integrator comprises a first differential amplifier; and the second integrator comprises a second differential amplifier. ### Claim 48 (depends on 47) The system of claim 47, wherein the first differential amplifier has differential input node terminals and differential output node terminals with resistor/capacitor (RC) feedback networks coupled between the differential output node terminals and the differential input node terminals. ### Claim 49 (depends on 48) The system of claim 48, wherein the second differential amplifier has differential input node terminals and differential output node terminals with RC feedback networks coupled between the differential output node terminals and the differential input node terminals, wherein the RC feedback networks of the second differential amplifier, in operation, provide virtual ground nodes; and the differential output node terminals of the first differential amplifier are coupled to the virtual ground nodes of the second differential amplifier via respective capacitances and switches of the plurality of switching circuits.