# US 2021/0242872 A1 · All-digital voltage monitor (advm) with single-cycle latency > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242872 A1 - Document ID: US20210242872A1 - Status: Published application - Kind: A1 - Application number: 17/020,667 - Filed: 2020-09-14 - Published: 2021-08-05 - Earliest claimed: 2020-02-05 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Suyoung Bang; Eric Samson; Wootaek Lim; Charles Augustine; Muhammad Khellah - Web page: https://patentgrep.com/patent/US20210242872A1 ## CPC - G06F 30/394: Routing (G06F30/396 takes precedence) - H03L 7/0814: {the phase shifting device being digitally controlled} - G04F 10/005: {Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60)} - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - H03M 1/00: Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code. ## Claims ### Claim 1 An apparatus comprising: a power supply node to provide a voltage and/or current; a clock node to provide a clock; and a voltage monitor coupled to the power supply node and the clock node, wherein the voltage monitor includes samplers that provide multi-bit resolution of the voltage on the power supply node in a single cycle of the clock. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the voltage monitor generates an output that represents a current voltage state of the voltage on the power supply node as a digital thermometer code or Gray code. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the voltage monitor is to monitor a range of voltage 7change of the voltage on the power supply node, wherein the range is greater than 400 mV. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the voltage monitor is to sample a voltage droop of the voltage on the power supply node. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the voltage monitor includes bubble suppression logic gates. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the voltage monitor is part of a digital standard library which complies with an automatic place and route scheme. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the voltage monitor is to apply polarity inversion of a code from a delay line, wherein the polarity inversion is applied ever other cycle of the clock. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the voltage monitor comprises: a clock divider to divide a frequency of the clock on the clock node and to generate a frequency divided clock; and a time-to-digital converter coupled to the clock divider and the power supply node, wherein the time-to-digital converter captures changes in voltage on the power supply node into a code. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the code is received by a power management unit. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the time-to-digital converter has a latency of one cycle of the clock on the clock node. ### Claim 11 (depends on 8) The apparatus of claim 8, wherein the clock divider has a divider ratio of 2, 4, or 8. ### Claim 12 (depends on 8) The apparatus of claim 8, wherein the time-to-digital converter comprises a delay chain comprising delay cells, wherein the delay chain is to receive the frequency divided clock at an input of the delay chain. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the voltage monitor comprises a plurality of sequential circuitries, wherein each of the sequential circuitries is coupled to an output of an individual delay cell of the delay chain. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the voltage monitor comprises a selection circuitry coupled to the plurality of sequential circuitries, wherein the selection circuitry includes a multiple of multiplexers, wherein each multiplexer is coupled to an individual sequential circuitry of the plurality of sequential circuitries. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the voltage monitor comprises logic to suppress metastability-induced bubble in outputs of the selection circuitry. ### Claim 16 An apparatus comprising: a voltage monitor coupled to a power supply node and a clock node, wherein the voltage monitor includes samplers that provide multi-bit resolution of a voltage on the power supply node in a single cycle of a clock on the clock node; and a power management controller to receive an output of the voltage monitor and adjusts a frequency of operation of a processor core according to the output. ### Claim 17 (depends on 17) The apparatus of claim 17, wherein the voltage monitor generates an output that represents a current voltage state of the voltage on the power supply node as a digital thermometer code or Gray code. ### Claim 18 A system comprising: a memory; a processor coupled to the memory; and a wireless interface to allow the processor to communicate with another device, wherein the processor includes: a power supply node to provide a voltage and/or current; a clock node to provide a clock; and a voltage monitor coupled to the power supply node and the clock node, wherein the voltage monitor includes samplers that provide multi-bit resolution of the voltage on the power supply node in a single cycle of the clock. ### Claim 19 (depends on 18) The system of claim 18, wherein the processor includes a power management controller to receive an output of the voltage monitor and adjusts a frequency of operation of a processor core according to the output. ### Claim 20 (depends on 18) The system of claim 18, wherein the processor includes a pin which provides a code from the voltage monitor, wherein the code indicates changes to the voltage on the power supply node.