# US 2021/0242862 A1 · Systems and Methods for Generating a Controllable-Width Pulse Signal

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- Number: US 2021/0242862 A1
- Document ID: US20210242862A1
- Status: Published application
- Kind: A1
- Application number: 17/233,735
- Filed: 2021-04-19
- Published: 2021-08-05
- Earliest claimed: 2019-06-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Ruey-Bin Sheen; Ming Hsien Tsai; Chih-Hsien Chang; Tsung-Hsien Tsai
- Web page: https://patentgrep.com/patent/US20210242862A1

## CPC

- H03K 5/14: by the use of delay lines (H03K5/133 takes precedence)
- G04F 5/00: Apparatus for producing preselected time intervals for use as timing standards (generating clock signals for electric digital computers G06F1/04)
- G04F 10/005: {Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60)}
- H03K 5/131: Digitally controlled
- H03K 5/135: by the use of time reference signals, e.g. clock signals
- H03K 2005/00058: {controlled by a digital setting}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S)

## Abstract

Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

## Claims

### Claim 1

A circuit for generating a pulse output having a controllable pulse width, comprising:
a delay line having a plurality of stages;
a delay per stage calculation circuit configured to determine a per-stage delay of the delay line;
a pulse generation circuit configured to generate the pulse output by using the delay line and based on the per-stage delay;
wherein the pulse generation circuit selectively accesses outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the delay per stage calculation circuit is configured to determine the per-stage delay of the delay line using a first clock input; wherein the delay line receives a second clock input; and wherein a frequency of the second clock input is substantially lower than a frequency of the first clock input.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the second clock frequency is less than 10% of the first clock frequency.

### Claim 4 (depends on 1)

The circuit of claim 1, further comprising:
a replica delay line having stages substantially similar to the delay line;
wherein the delay per stage calculation circuit determines the per-stage delay of the delay line based on operation of the replica delay line receiving a first clock input.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein the delay per stage calculation circuit does not control the delay line in determining the per-stage delay of the delay line.

### Claim 6 (depends on 4)

The circuit of claim 4, wherein the replica delay line has an identical number of stages as the delay line.

### Claim 7 (depends on 1)

The circuit of claim 1, further comprising an SR flip flop that receives the outputs of the two stages and generates the pulse output.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein the circuit is configured to determine the per-stage delay exactly one time per initialization of the circuit.

### Claim 9 (depends on 1)

The circuit of claim 1, wherein the two stages are selected based on a selected pulse output width and the per-stage delay.

### Claim 10

A method of generating a pulse output having a controllable pulse width, comprising:
determining a per-stage delay of a delay line based on a first clock input;
generating the pulse output using the delay line based on the per-stage delay by providing the delay line a second clock input, the second clock input having a lower frequency than the first clock input
generating the pulse output from the frequency of the second clock input, wherein the frequency of the second clock input is substantially lower than the frequency of the first clock frequency used to determine the per-stage delay.

### Claim 11 (depends on 10)

The method of claim 10, wherein determining the per-stage delay of the delay line comprises:
providing the first clock input to a replica delay line having stages substantially similar to the delay line;
wherein the per-stage delay of the delay line is based on operation of the replica delay line receiving the first clock input.

### Claim 12 (depends on 10)

The method of claim 10, wherein generating the pulse output comprises:
selectively accessing outputs of two stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.

### Claim 13 (depends on 12)

The method of claim 12, wherein the two stages are selected based on a selected pulse output width and the per-stage delay.

### Claim 14 (depends on 10)

The method of claim 10, wherein the second clock frequency is less than 10% of the first clock frequency.

### Claim 15 (depends on 11)

The method of claim 11, wherein the replica delay line has an identical number of stages as the delay line.

### Claim 16 (depends on 10)

The method of claim 10, wherein determining the per-stage delay of the delay line further comprises:
determining the per-stage delay exactly one time per initialization of the circuit.

### Claim 17

A circuit for generating a pulse output having a pulse width of a controllable length of time, comprising:
a delay line and a replica delay line each having a plurality of stages;
a delay per stage calculation circuit configured to determine a per-stage delay of the delay line by using a first clock input, wherein the determining a per-stage delay of the delay line is based on operation of the replica delay line;
a pulse generation circuit configured to generate the pulse output by using the delay line and based on the per-stage delay, wherein the delay line receives a second clock input.

### Claim 18 (depends on 17)

The circuit of claim 17, wherein the replica delay line has stages substantially similar to the delay line, and wherein the delay per stage calculation circuit does not control the delay line in determining the per-stage delay of the delay line.

### Claim 19 (depends on 17)

The circuit of claim 17, wherein the frequency of the second clock input is substantially lower than the frequency of the first clock frequency.

### Claim 20 (depends on 19)

The circuit of claim 19, wherein the second clock frequency is less than 10% of the first clock frequency.