# US 2021/0242846 A1 · Amplifier circuit, corresponding comparator device and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242846 A1 - Document ID: US20210242846A1 - Status: Published application - Kind: A1 - Application number: 17/141,812 - Filed: 2021-01-05 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: STMicroelectronics S.r.l. - Applicants: STMicroelectronics S.r.l. - Inventors: Roberto Modaffari - Web page: https://patentgrep.com/patent/US20210242846A1 ## CPC - G01R 19/0038: {Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)} - H03F 3/45197: {Pl types (H03F3/45224, H03F3/45251 take precedence)} - H03K 5/24: the characteristic being amplitude - H03K 5/2481: {with at least one differential stage} - H03F 2200/375: Circuitry to compensate the offset being present in an amplifier - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03F: AMPLIFIERS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A preamplifier circuit comprises a first pair of transistors and a second pair of transistors having current flow paths therethrough coupled at first and second output nodes and providing first and second current flow lines intermediate a supply node and ground. The two pairs of transistors comprise: first and second input transistors located intermediate the outputs nodes and one of the supply node and ground providing respective input nodes, first and second load transistors intermediate the output nodes and the other of the supply node and ground. The load transistors have control terminals capacitively coupled to the other of the supply node and ground and a reset switch arrangement is provided periodically activatable to short the first output node, the second output node as well as the control terminals of the first load transistor and the second load transistor. ## Claims ### Claim 1 A circuit, comprising: a first input transistor having conductive terminals respectively coupled to a first output node and one of a supply node and ground, the first input transistor having a control terminal coupled to a first input node; a second input transistor having conductive terminals respectively coupled to a second output node and the one of the supply node and ground, the second input transistor having a control terminal coupled to a second input node; a capacitance having a first side coupled to the other of the supply node and ground and having a second side; a first load transistor having conductive terminals respectively coupled to the first output node and the other of the supply node and ground, the first load transistor having a control terminal coupled to the second side of the capacitance; a second load transistor having conductive terminals respectively coupled to the second output node and the other of the supply node and ground, the second load transistor having a control terminal coupled to the second side of the capacitance; and a reset switch circuit configured to, in response to being activated, short the first output node, the second output node, the control terminal of the first load transistor and the control terminal of the second load transistor. ### Claim 2 (depends on 1) The circuit of claim 1, comprising: a current supply source having an anode and a cathode, wherein one of the anode and the cathode is coupled to one of the supply node and ground, and wherein the other of the anode and the cathode is configured to sink or source both a first current flowing through the first input transistor and the first load transistor and a second current flowing through the second input transistor and the second load transistor. ### Claim 3 (depends on 1) The circuit of claim 1, wherein the first input transistor and the second input transistor have a first polarity in common and the first load transistor and the second load transistor have a second polarity, opposite the first polarity, in common. ### Claim 4 (depends on 1) The circuit of claim 1, wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are field-effect transistors (FETs). ### Claim 5 (depends on 4) The circuit of claim 4, wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are metal-oxide-semiconductor FETs (MOSFETs). ### Claim 6 (depends on 1) The circuit of claim 1, wherein the reset switch circuit is configured to, in response to being activated, set the first output node to zero voltage. ### Claim 7 A comparator, comprising: a first input transistor having conductive terminals respectively coupled to a first output node and one of a supply node and ground, the first input transistor having a control terminal coupled to a first input node; a second input transistor having conductive terminals respectively coupled to a second output node and the one of the supply node and ground, the second input transistor having a control terminal coupled to a second input node; a capacitance having a first side coupled to the other of the supply node and ground and having a second side; a first load transistor having conductive terminals respectively coupled to the first output node and the other of the supply node and ground, the first load transistor having a control terminal coupled to the second side of the capacitance; a second load transistor having conductive terminals respectively coupled to the second output node and the other of the supply node and ground, the second load transistor having a control terminal coupled to the second side of the capacitance; a reset switch circuit configured to, in response to being activated, short the first output node, the second output node, the control terminal of the first load transistor and the control terminal of the second load transistor; and a latch circuit having input nodes coupled to the first output node and the second output node, respectively, and output nodes, wherein in response to receiving a first input signal at the first input node and a second input signal at the second input node, the latch circuit is configured to provide between the respective output nodes a differential latched signal that based on an outcome of a comparison between the first input signal and the second input signal. ### Claim 8 (depends on 7) The comparator of claim 7, comprising: a current supply source having an anode and a cathode, wherein one of the anode and the cathode is coupled to one of the supply node and ground, and wherein the other of the anode and the cathode is configured to sink or source both a first current flowing through the first input transistor and the first load transistor and a second current flowing through the second input transistor and the second load transistor. ### Claim 9 (depends on 7) The comparator of claim 7, wherein the first input transistor and the second input transistor have a first polarity in common and the first load transistor and the second load transistor have a second polarity, opposite the first polarity, in common. ### Claim 10 (depends on 7) The comparator of claim 7, wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are field-effect transistors (FETs). ### Claim 11 (depends on 10) The comparator of claim 10, wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are metal-oxide-semiconductor FETs (MOSFETs). ### Claim 12 (depends on 7) The comparator of claim 7, wherein the reset switch circuit is configured to, in response to being activated, set the first output node to zero voltage. ### Claim 13 A method, comprising: supplying a first input signal to a first input node and a second input signal to a second input node, wherein: the first input node is coupled to a control terminal of a first input transistor, and the first input transistor has conductive terminals respectively coupled to a first output node and one of a supply node and ground, and the second input node is coupled to a control terminal of a second input transistor, and the second input transistor has conductive terminals respectively coupled to a second output node and the one of the supply node and ground, outputting an output signal over a first output node and a second output node, wherein: the first output node is coupled to a first conductive terminal of a first load transistor, the first load transistor having a second conductive terminal coupled to the other of the supply node and ground and a control terminal coupled to a first side of a capacitance, and the capacitance having a second side coupled to the other of the supply node and ground, and the second output node is coupled to a first conductive terminal of a second load transistor, the second load transistor having a second conductive terminal coupled to the other of the supply node and ground and a control terminal coupled to the first side of the capacitance, and activating a reset switch circuit to short the first output node, the second output node, the control terminal of the first load transistor and the control terminal of the second load transistor. ### Claim 14 (depends on 13) The method of claim 13, comprising: setting the output signal to zero voltage in response to activating, at a subsequent activation event, the reset switch circuit. ### Claim 15 (depends on 14) The method of claim 14, comprising: separating subsequent activation events of the reset switch circuit by respective output signal integration intervals; and collecting output signals over the first and second output nodes at respective ends of the output signal integration intervals. ### Claim 16 (depends on 13) The method of claim 13, wherein one of an anode and a cathode of a current supply source is coupled to one of the supply node and ground, and the other of the anode and the cathode of the current supply source sinks or sources both a first current flowing through the first input transistor and the first load transistor and a second current flowing through the second input transistor and the second load transistor. ### Claim 17 (depends on 13) The method of claim 13, wherein the first input transistor and the second input transistor have a first polarity in common and the first load transistor and the second load transistor have a second polarity, opposite the first polarity, in common. ### Claim 18 (depends on 13) The method of claim 13, wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are field-effect transistors (FETs). ### Claim 19 (depends on 18) The method of claim 18, wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are metal-oxide-semiconductor FETs (MOSFETs).