# US 2021/0242842 A1 · Power amplifier circuit and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242842 A1 - Document ID: US20210242842A1 - Status: Published application - Kind: A1 - Application number: 17/168,618 - Filed: 2021-02-05 - Published: 2021-08-05 - Earliest claimed: 2020-02-05 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Hiroaki TOKUYA; Hideyuki SATO; Fumio HARIMA; Kenichi SHIMAMOTO; Satoshi TANAKA; Takayuki KAWANO; Ryoki SHIKISHIMA; Atsushi KUROKAWA - Web page: https://patentgrep.com/patent/US20210242842A1 ## CPC - H03F 3/245: {with semiconductor devices only} - H03F 1/302: {in bipolar transistor amplifiers (H03F1/303, H03F1/305, H03F1/307 take precedence)} - H03F 3/195: in integrated circuits - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H03F 2200/451: the amplifier being a radio frequency amplifier - H10D 10/821: {Vertical heterojunction BJTs} - H10D 64/231: {Emitter or collector electrodes for bipolar transistors} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/66: Conductive materials thereof - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H03F: AMPLIFIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view. ## Claims ### Claim 1 A power amplifier circuit comprising: a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and having a base configured to be supplied with a first current which is a first part of a control current, the second transistor being configured to supply a bias current based on the first current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a second part of the control current and an emitter configured to output a third current based on the second current; a first metal member electrically connected to an emitter of the first transistor, said first metal member being disposed to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second metal member disposed to overlap a second disposition area in which the third transistor is disposed in the plan view. ### Claim 2 (depends on 1) The power amplifier circuit according to claim 1, further comprising: a first insulating film disposed between the first transistor and the first metal member; and a second insulating film disposed between the second transistor and the second metal member, wherein the first metal member is electrically connected to the emitter of the first transistor through a first cavity disposed in the first insulating film, and the second metal member is electrically connected to an emitter of the second transistor through a second cavity disposed in the second insulating film. ### Claim 3 (depends on 1) The power amplifier circuit according to claim 1, wherein the second metal member is disposed to overlap an emitter of the second transistor in the plan view. ### Claim 4 (depends on 2) The power amplifier circuit according to claim 2, wherein the second metal member is disposed to overlap the emitter of the second transistor in the plan view. ### Claim 5 (depends on 1) The power amplifier circuit according to claim 1, wherein each of the first metal member and the second metal member is a bump. ### Claim 6 (depends on 2) The power amplifier circuit according to claim 2, wherein each of the first metal member and the second metal member is a bump. ### Claim 7 (depends on 3) The power amplifier circuit according to claim 3, wherein each of the first metal member and the second metal member is a bump. ### Claim 8 (depends on 1) The power amplifier circuit according to claim 1, wherein the first metal member and the second metal member have a substantially identical thickness in a direction perpendicular to a principal surface of the semiconductor substrate. ### Claim 9 (depends on 2) The power amplifier circuit according to claim 2, wherein the first metal member and the second metal member have a substantially identical thickness in a direction perpendicular to a principal surface of the semiconductor substrate. ### Claim 10 (depends on 3) The power amplifier circuit according to claim 3, wherein the first metal member and the second metal member have a substantially identical thickness in a direction perpendicular to a principal surface of the semiconductor substrate. ### Claim 11 (depends on 1) A semiconductor device comprising: a semiconductor chip including the power amplifier circuit according to claim 1; a module substrate on which the semiconductor chip is mounted; and a resin mold disposed around the semiconductor chip. ### Claim 12 (depends on 2) A semiconductor device comprising: a semiconductor chip including the power amplifier circuit according to claim 2; a module substrate on which the semiconductor chip is mounted; and a resin mold disposed around the semiconductor chip. ### Claim 13 A power amplifier circuit comprising: a first transistor disposed on a semiconductor substrate; a bias circuit configured to be supplied with a control current and to supply a bias current based on the control current to the first transistor; a first metal member electrically connected to an emitter of the first transistor, said first metal member being disposed to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; a control circuit connected to the bias circuit and configured to supply the control current to the bias circuit; a diode disposed on the semiconductor substrate and having an anode connected to the control circuit and a cathode connected to ground; and a third metal member disposed to overlap a third disposition area in which the diode is disposed in the plan view, wherein the control circuit is configured to detect a characteristic variation of the diode and supply the control current controlled in accordance with the characteristic variation to the bias circuit. ### Claim 14 (depends on 13) The power amplifier circuit according to claim 13, further comprising: a first insulating film disposed between the first transistor and the first metal member; and a third insulating film disposed between the diode and the third metal member, wherein the first metal member is electrically connected to the emitter of the first transistor through a first cavity disposed in the first insulating film, and the third metal member is electrically connected to the diode through a third cavity disposed in the third insulating film. ### Claim 15 (depends on 13) The power amplifier circuit according to claim 13, wherein each of the first metal member and the third metal member is a bump. ### Claim 16 (depends on 14) The power amplifier circuit according to claim 14, wherein each of the first metal member and the third metal member is a bump. ### Claim 17 (depends on 13) The power amplifier circuit according to claim 13, wherein the first metal member and the third metal member have a substantially identical thickness in a direction perpendicular to a principal surface of the semiconductor substrate. ### Claim 18 (depends on 14) The power amplifier circuit according to claim 14, wherein the first metal member and the third metal member have a substantially identical thickness in a direction perpendicular to a principal surface of the semiconductor substrate. ### Claim 19 (depends on 13) A semiconductor device comprising: a semiconductor chip including the power amplifier circuit according to claim 13; a module substrate on which the semiconductor chip is mounted; and a resin mold disposed around the semiconductor chip. ### Claim 20 (depends on 14) A semiconductor device comprising: a semiconductor chip including the power amplifier circuit according to claim 14; a module substrate on which the semiconductor chip is mounted; and a resin mold disposed around the semiconductor chip.