# US 2021/0242837 A1 · Transimpedance amplifier for converting electrical currents to voltages > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242837 A1 - Document ID: US20210242837A1 - Status: Published application - Kind: A1 - Application number: 16/778,895 - Filed: 2020-01-31 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: NVIDIA Corporation - Applicants: Nvidia Corporation - Inventors: Sanquan Song; John Poulton; Carl Thomas Gray - Web page: https://patentgrep.com/patent/US20210242837A1 ## CPC - H03F 1/086: {with FET's} - H03F 1/0272: {by using a signal derived from the output signal} - H03F 1/26: Modifications of amplifiers to reduce influence of noise generated by amplifying elements - H03F 3/082: {with FET's (H03F3/085 takes precedence)} - H04B 10/693: {Arrangements for optimizing the preamplifier in the receiver} - H03F 2200/372: Noise reduction and elimination in amplifier - H03F: AMPLIFIERS - H04B: TRANSMISSION ## Abstract The disclosure provides an improved transimpedance amplifier (TIA) that can operate at a higher bandwidth and lower noise compared to conventional TIAs. The TIA employs a data path with both feedback impedance and feedback capacitance for improved performance. The feedback impedance includes at least two resistors in series and at least one shunt capacitor, coupled between the at least two resistors, that helps to extend the circuit bandwidth and improve SNR at the same time. The capacitance value of the shunt capacitor can be selected based on both the bandwidth and noise. In one example, the TIA includes: (1) a biasing path, and (2) a data path, coupled to the biasing path, including multiple inverter stages and at least one feedback capacitance coupled across an even number of the multiple inverter stages. An optical receiver and a circuit having the TIA are also disclosed. ## Claims ### Claim 1 A transimpedance amplifier (TIA), comprising: a biasing path; and a data path, coupled to the biasing path, including multiple inverter stages and at least one feedback capacitance coupled across an even number of the multiple inverter stages. ### Claim 2 (depends on 1) The TIA as recited in claim 1, wherein alternating ones of the multiple inverter stages include feedback impedance. ### Claim 3 (depends on 2) The TIA as recited in claim 2, wherein each of the feedback impedances includes multiple feedback resistors coupled in series and at least one shunt capacitor coupled between the multiple feedback resistors. ### Claim 4 (depends on 3) The TIA as recited in claim 3, wherein a number of the multiple feedback resistors coupled in series is two. ### Claim 5 (depends on 1) The TIA as recited in claim 1, wherein the data path includes at least three inverter stages and multiple feedback capacitances, wherein a different one of the feedback capacitances is coupled across a different even numbered combination of the at least three inverter stages. ### Claim 6 (depends on 5) The TIA as recited in claim 5, wherein the at least three inverter stages are coupled in series and alternating ones of the at least three inverter stages include a feedback impedance having multiple feedback resistors coupled in series and a shunt capacitor coupled between the multiple feedback resistors. ### Claim 7 (depends on 1) The TIA as recited in claim 1, wherein the data path includes a first, a second, and a third inverter stage, a first feedback capacitance coupled across the first and the second inverter stages, a second feedback capacitance coupled across the second and the third inverter stages, and each of the first and the third inverter stages include a feedback impedance, wherein each of the feedback impedances for the first and the third inverters include at least two feedback resistors coupled in series and at least one shunt capacitor coupled between the two feedback resistors. ### Claim 8 A circuit, comprising: a processor, and a transimpedance amplifier (TIA), coupled to the processor, including a data path having multiple inverter stages and at least one feedback capacitance coupled across an even number of the multiple inverter stages. ### Claim 9 (depends on 8) The circuit as recited in claim 8, further comprising a bus, wherein the TIA is coupled to the processor via the bus. ### Claim 10 (depends on 9) The circuit as recited in claim 9, further comprising a sensing amplifier and a deserializer, wherein the sensing amplifier is coupled to an output of the TIA, the deserializer is coupled to an output of the sensing amplifier and the bus, and the processor is coupled to the bus. ### Claim 11 (depends on 8) The circuit as recited in claim 8, wherein the circuit is located on a single chip. ### Claim 12 (depends on 11) The circuit as recited in claim 11, wherein the processor is a graphics processing unit. ### Claim 13 (depends on 8) The circuit as recited in claim 8, wherein the data path includes at least three inverter stages and multiple feedback capacitances, wherein a different one of the feedback capacitances is coupled across a different even numbered combination of the at least three inverters. ### Claim 14 (depends on 13) The circuit as recited in claim 13, wherein each alternating one of the at least three inverters includes a feedback impedance having multiple feedback resistors coupled in series and a shunt capacitor coupled between the multiple feedback resistors. ### Claim 15 An optical receiver, comprising: a photodetector; and a transimpedance amplifier (TIA) coupled to the photodetector and including a data path having multiple inverter stages and at least one feedback capacitance coupled across an even number of the multiple inverter stages. ### Claim 16 (depends on 15) The optical receiver as recited in claim 15, further comprising an optical waveguide coupled to the photodetector, wherein the photodetector receives light from the waveguide and converts the light to an electrical current that is received by the TIA. ### Claim 17 (depends on 15) The optical receiver as recited in claim 15, wherein the data path includes at least three inverters and multiple feedback capacitances, wherein a different one of the feedback capacitances is coupled across a different even numbered combination of the at least three inverters. ### Claim 18 (depends on 15) The optical receiver as recited in claim 15, wherein the photodetector and the TIA are located on a single chip. ### Claim 19 A method of operating an optical receiver having a transimpedance amplifier (TIA), comprising: receiving optical data; converting the optical data to an electrical current; and converting the electrical current to an electrical voltage employing the TIA, wherein the converting includes extending a bandwidth of the TIA and increasing a signal to noise ratio of the TIA employing feedback impedance, and further increasing the bandwidth of the TIA employing feedback capacitance. ### Claim 20 (depends on 19) The method as recited in claim 19 further comprising reducing a DC component of the electrical current employing a biasing path of the TIA.