# US 2021/0242836 A1 · Power amplifier circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242836 A1 - Document ID: US20210242836A1 - Status: Published application - Kind: A1 - Application number: 17/167,406 - Filed: 2021-02-04 - Published: 2021-08-05 - Earliest claimed: 2020-02-05 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Hideyuki SATO; Koshi HIMEDA - Web page: https://patentgrep.com/patent/US20210242836A1 ## CPC - H03F 1/08: Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements (wide-band amplifiers with inter-stage coupling networks incorporating these impedances H03F1/42) - H03F 1/302: {in bipolar transistor amplifiers (H03F1/303, H03F1/305, H03F1/307 take precedence)} - H03F 1/083: {in transistor amplifiers (H03F1/10 - H03F1/22 take precedence)} - H03F 3/195: in integrated circuits - H03F 3/213: in integrated circuits - H03F 3/245: {with semiconductor devices only} - H10D 10/821: {Vertical heterojunction BJTs} - H10D 84/60: characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs (H10D84/40 takes precedence) - H03F 2200/447: the amplifier being protected to temperature influence - H03F 2200/451: the amplifier being a radio frequency amplifier - H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/66: Conductive materials thereof - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H03F: AMPLIFIERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate. ## Claims ### Claim 1 A power amplifier circuit comprising: a first transistor on a semiconductor substrate; a second transistor on the semiconductor substrate, the second transistor having a base supplied with a first current and being configured to supply a bias current based on the first current to the first transistor; a current output circuit element on the semiconductor substrate, the current output circuit element being supplied with a second current and being configured to output a third current based on the second current, the second current increasing in accordance with a rise in temperature; and wiring comprising a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked on top of each other, wherein the first current and the second current are part of a control current, and wherein, as seen in a plan view of the semiconductor substrate: the plurality of metal layers overlap the first transistor and an area between the first transistor and the current output circuit element, and at least one of the plurality of metal layers further overlaps the current output circuit element. ### Claim 2 (depends on 1) The power amplifier circuit according to claim 1, wherein all of the plurality of metal layers further overlap the current output circuit element. ### Claim 3 (depends on 1) The power amplifier circuit according to claim 1, wherein an uppermost one of the plurality of metal layers is a bump. ### Claim 4 (depends on 1) The power amplifier circuit according to claim 1, wherein at least one of the plurality of metal layers comprises, at a position that overlaps the current output circuit element, a protrusion that extends in a thickness direction of the semiconductor substrate toward the current output circuit element. ### Claim 5 (depends on 2) The power amplifier circuit according to claim 2, wherein at least one of the plurality of metal layers comprises, at a position that overlaps the current output circuit element, a protrusion that extends in a thickness direction of the semiconductor substrate toward the current output circuit element. ### Claim 6 (depends on 2) The power amplifier circuit according to claim 2, wherein at least one of the plurality of metal layers comprises, at a position that overlaps the current output circuit element, a protrusion that extends in a thickness direction of the semiconductor substrate toward the current output circuit element. ### Claim 7 (depends on 4) The power amplifier circuit according to claim 4, wherein the wiring is electrically connected to the current output circuit element. ### Claim 8 A power amplifier circuit comprising: a first transistor on a semiconductor substrate; a second transistor on the semiconductor substrate, the semiconductor substrate having a base supplied with a first current and being configured to supply a bias current based on the first current to the first transistor; a current output circuit element on the semiconductor substrate, the current output circuit element being supplied with a second current and being configured to output a third current based on the second current, the second current increasing in accordance with a rise in temperature; a third transistor on the semiconductor substrate, the third transistor having a collector supplied with a fourth current and an emitter configured to output the second current based on the fourth current; and wiring comprising a plurality of metal layers that are electrically connected to an emitter of the first transistor, and that are stacked on top of each other, wherein the first current, the second current, and the fourth current are part of a control current, and wherein as seen in a plan view of the semiconductor substrate: the plurality of metal layers overlap the first transistor and an area between the first transistor and an area defined by the second transistor, the current output circuit element, and the third transistor, at least one of the plurality of metal layers further overlaps the area defined by the second transistor, the current output circuit element, and the third transistor. ### Claim 9 (depends on 8) The power amplifier circuit according to claim 8, wherein all of the plurality of metal layers further overlap the area defined by the second transistor, the current output circuit element, and the third transistor. ### Claim 10 (depends on 8) The power amplifier circuit according to claim 8, wherein an uppermost one of the plurality of metal layers is a bump. ### Claim 11 (depends on 9) The power amplifier circuit according to claim 9, wherein an uppermost one of the plurality of metal layers is a bump. ### Claim 12 (depends on 8) The power amplifier circuit according to claim 8, wherein at least one of the plurality of metal layers comprises, at a position that overlaps the current output circuit element, a protrusion that extends in a thickness direction of the semiconductor substrate toward the current output circuit element. ### Claim 13 (depends on 9) The power amplifier circuit according to claim 9, wherein at least one of the plurality of metal layers comprises, at a position that overlaps the current output circuit element, a protrusion that extends in a thickness direction of the semiconductor substrate toward the current output circuit element. ### Claim 14 (depends on 10) The power amplifier circuit according to claim 10, wherein at least one of the plurality of metal layers comprises, at a position that overlaps the current output circuit element, a protrusion that extends in a thickness direction of the semiconductor substrate toward the current output circuit element. ### Claim 15 (depends on 12) The power amplifier circuit according to claim 12, wherein the wiring is electrically connected to the current output circuit element. ### Claim 16 (depends on 8) The power amplifier circuit according to claim 8, wherein the at least one metal layer overlaps an area between the first transistor and the second transistor. ### Claim 17 (depends on 15) The power amplifier circuit according to claim 15, wherein: a first of the plurality of metal layers overlaps the first transistor and the area between the first transistor and the area defined by the second transistor, the current output circuit element, and the third transistor, and a second of the plurality of metal layers overlaps the first transistor and the area between the first transistor and the second transistor. ### Claim 18 A power amplifier circuit comprising: a first transistor on a semiconductor substrate; a second transistor on the semiconductor substrate, the second transistor having a base supplied with a first current and being configured to supply a bias current based on the first current to the first transistor; a current output circuit element on the semiconductor substrate, the current output circuit element being supplied with a second current and being configured to output a third current based on the second current, the second current increasing in accordance with a rise in temperature; and wiring comprising a plurality of metal layers that are electrically connected to a collector of the first transistor, and that are stacked one on top of each other, wherein the first current and the second current are part of a control current, and wherein, as seen in a plan view of the semiconductor substrate: the plurality of metal layers overlap the first transistor and an area between the first transistor and the current output circuit element, and at least one of the plurality of metal layers overlaps the second transistor. ### Claim 19 (depends on 18) The power amplifier circuit according to claim 18, wherein an uppermost one of the metal layers is a bump. ### Claim 20 (depends on 18) The power amplifier circuit according to claim 18, wherein at least one of the plurality of metal layers comprises, at a position that overlaps the current output circuit element, a protrusion that extends in a thickness direction of the semiconductor substrate, toward the current output circuit element.