# US 2021/0242780 A1 · Methods and apparatus to adjust an operating mode of a power converter

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0242780 A1
- Document ID: US20210242780A1
- Status: Published application
- Kind: A1
- Application number: 16/779,259
- Filed: 2020-01-31
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Janne Matias Pahkala; Antti Juhani Korhonen
- Web page: https://patentgrep.com/patent/US20210242780A1

## CPC

- H02M 3/1582: {Buck-boost converters (H02M3/1584 takes precedence)}
- H03K 7/06: Frequency or rate modulation, i.e. PFM or PRM
- H03K 7/08: Duration or width modulation {; Duty cycle modulation}
- H02M 1/0032: {Control circuits allowing low power mode operation, e.g. in standby mode}
- H02M 3/1566: {with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation}
- H02M 3/158: including plural semiconductor devices as final control devices for a single load
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to adjust an operating mode of a power converter. An example apparatus includes a first transistor having a gate terminal, a first current terminal, and a second current terminal, the first current terminal to be coupled to a second transistor and an inductor of a power converter, a capacitor coupled to the second current terminal, a logic gate having a first logic gate input, a second logic gate input, and a logic gate output, the logic gate output coupled to the gate terminal, a comparator having a comparator input and a comparator output, the comparator input coupled to the capacitor and the second current terminal, a multiplexer coupled to the comparator output, a first flip-flop coupled to the multiplexer and the second logic gate input, and a second flip-flop coupled to the multiplexer and the first flip-flop.

## Claims

### Claim 1

An apparatus comprising:
a first transistor having a gate terminal, a first current terminal, and a second current terminal, the first current terminal to be coupled to a second transistor and an inductor of a power converter;
a capacitor coupled to the second current terminal;
a logic gate having a first logic gate input, a second logic gate input, and a logic gate output, the logic gate output coupled to the gate terminal;
a comparator having a comparator input and a comparator output, the comparator input coupled to the capacitor and the second current terminal;
a multiplexer coupled to the comparator output;
a first flip-flop coupled to the multiplexer and the second logic gate input; and
a second flip-flop coupled to the multiplexer and the first flip-flop.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the logic gate is a first logic gate, the first flip-flop has a first flip-flop input, a second flip-flop input, and a flip-flop output, the multiplexer has a multiplexer selection input, the flip-flop output coupled to the second logic gate input and the multiplexer selection input, and further including a second logic gate having a third logic gate input and a second logic gate output, the third logic gate input coupled to the second logic gate input, the flip-flop output, and the multiplexer selection input, the second logic gate output coupled to the first flip-flop input.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the first logic gate is an AND logic gate, the first logic gate input is a non-inverted input, the second logic gate input is an inverted input, and the second logic gate is an inverter.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the multiplexer has a first multiplexer input, a second multiplexer input, a multiplexer selection input, and a multiplexer output, the second flip-flop has a first flip-flop input, a second flip-flop input, and a flip-flop output, the first flip-flop input coupled to the multiplexer output, the second flip-flop input coupled to the first flip-flop, the flip-flop output coupled to the second multiplexer input, and further including a control logic circuit having a control logic input and a control logic output, the control logic input coupled to the flip-flop output and the second multiplexer input, the control logic output coupled to the first flip-flop and the second flip-flop input.

### Claim 5 (depends on 4)

The apparatus of claim 4, further including a driver circuit having a driver circuit input and a driver circuit output, the driver circuit input coupled to the control logic output, the driver circuit output coupled to the first logic gate input, the driver circuit output configured to be coupled to the second transistor.

### Claim 6

An apparatus comprising:
a control logic circuit configured to:
generate a first control signal and a second control signal, the second control signal after the first control signal; and
adjust a first operating mode of a power converter to a second operating mode of the power converter in response to an assertion of a first logic signal; and
a signal comparator circuit including a comparator, the signal comparator circuit coupled to the control logic circuit, the signal comparator circuit configured to:
in response to the first control signal, sample an input of the comparator and assert a second logic signal in response to the input satisfying a threshold; and
in response to the second control signal, assert the first logic signal.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the first operating mode is a pulse-width modulation (PWM) mode and the second operating mode is a pulse-frequency modulation (PFM) mode.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the power converter includes an inductor and a first transistor having a first current terminal and a second current terminal, and the signal comparator circuit includes:
a second transistor having a third current terminal and a fourth current terminal, the third current terminal coupled to the first current terminal and to be coupled to the inductor, the fourth current terminal coupled to the input, the inductor to generate an inductor current, the inductor current to cause a voltage to be generated across the first current terminal and the second current terminal;
a capacitor coupled to the fourth current terminal and the input; and wherein
the comparator is configured to compare the voltage at the input and assert the second logic signal in response to the inductor current being less than a current threshold.

### Claim 9 (depends on 6)

The apparatus of claim 6, wherein the power converter includes a first transistor having a first current terminal, the input is a comparator input, the comparator having a comparator output, and the signal comparator circuit includes:
a second transistor having a second current terminal and a third current terminal, the second current terminal coupled to the first current terminal, the comparator input coupled to third current terminal;
a multiplexer coupled to the comparator output;
a first flip-flop coupled to the multiplexer and the control logic circuit; and
a second flip-flop coupled to the first flip-flop, the multiplexer, and the control logic circuit.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the control logic circuit has a control logic circuit input and a control logic circuit output, the multiplexer has a selection input, a first multiplexer input, a second multiplexer input, and a multiplexer output, the first flip-flop has a first flip-flop input, a first clock input, and a first flip-flop output, the second flip-flop has a second flip-flop input, a second clock input, and a second flip-flop output, and wherein:
the first multiplexer input is coupled to the comparator output;
the second multiplexer input is coupled to the second flip-flop output and the control logic circuit input;
the multiplexer output is coupled to the second flip-flop input; and
the first clock input is coupled to the second clock input and the control logic circuit output.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the first transistor has a first gate terminal, the second transistor has a second gate terminal, the power converter further including a third transistor having a third gate terminal and a fourth current terminal, the fourth current terminal coupled to the first current terminal, and further including:
a control logic circuit having a control logic circuit input and a control logic circuit output, the control logic circuit input coupled to a flip-flop output of the second flip-flop, the control logic circuit output coupled to a first flip-flop input of the first flip-flop and a second flip-flop input of the second flip-flop; and
a driver circuit having a driver circuit input, a first driver circuit output, and a second driver circuit output, the driver circuit input coupled to the control logic circuit output, the first driver circuit output coupled to the first gate terminal, the second driver circuit output coupled to the third gate terminal.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the first transistor has a first gate terminal, the second transistor has a second gate terminal, and the signal comparator circuit includes:
a first logic gate having a first logic gate input, a second logic gate input, and a first logic gate output, the first logic gate input coupled to the first gate terminal, the second logic gate input coupled to a first flip-flop output of the first flip-flop, the first logic gate output coupled to the second gate terminal; and
a second logic gate having a third logic gate input and a second logic gate output, the third logic gate input coupled to the second logic gate input and the first flip-flop output, the second logic gate output coupled to a first flip-flop input of the first flip-flop.

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein the threshold is a first threshold, the first transistor has a first gate terminal and the second transistor has a second gate terminal, and further including:
a logic gate having a logic gate output coupled to the second gate terminal, the logic gate configured to assert the second logic signal in response to the first control signal, the second logic signal to turn on the second transistor; and wherein
the multiplexer is configured to assert a third logic signal in response to the second logic signal being asserted and the first flip-flop asserting a fourth logic signal.

### Claim 14

A power conversion system comprising:
a power converter having a load terminal, the load terminal to be coupled to a load, the power converter including a transistor having a current terminal and a gate terminal;
a switch mode control circuit coupled to the current terminal and the gate terminal, the switch mode control circuit including a comparator, the switch mode control circuit configured to:
in response to a first control signal, sample an input of the comparator;
in response to the input satisfying a threshold, assert a first logic signal;
in response to a second control signal after the first control signal, assert a second logic signal in response to the assertion of the first logic signal; and
adjust a first operating mode of the power converter to a second operating mode of the power converter in response to the assertion of the second logic signal.

### Claim 15 (depends on 14)

The power conversion system of claim 14, wherein the power converter is a buck converter, the transistor is a first transistor, the current terminal is a first current terminal coupled to the switch mode control circuit, the gate terminal is a first gate terminal coupled to the switch mode control circuit, and the power converter further including:
a second transistor having a second current terminal and a second gate terminal, the second current terminal coupled to the first current terminal and the switch mode control circuit;
a first inductor terminal to be coupled to an inductor, the first inductor terminal coupled to the first current terminal, the second current terminal, and the switch mode control circuit; and
a second inductor terminal to be coupled to the inductor and the load terminal.

### Claim 16 (depends on 14)

The power conversion system of claim 14, wherein the first operating mode is a pulse-width modulation (PWM) mode and the second operating mode is a pulse-frequency modulation (PFM) mode.

### Claim 17 (depends on 14)

The power conversion system of claim 14, wherein the power converter includes an inductor, the current terminal is a first current terminal, the transistor is a first transistor having a second current terminal, and the switch mode control circuit includes:
a second transistor having a third current terminal and a fourth current terminal, the third current terminal coupled to the first current terminal and to be coupled to the inductor, the fourth current terminal coupled to the input, the inductor to generate an inductor current, the inductor current to cause a voltage to be generated across the first current terminal and the second current terminal; and wherein
the comparator is configured to compare the voltage at the input and assert the first logic signal in response to the inductor current being less than a current threshold.

### Claim 18 (depends on 14)

The power conversion system of claim 14, wherein the switch mode control circuit includes a driver circuit, a signal comparator circuit, and a control logic circuit, the driver circuit coupled to the signal comparator circuit and the control logic circuit, and wherein the driver circuit is configured to turn on the transistor in response to the first control signal and the second control signal.

### Claim 19 (depends on 14)

The power conversion system of claim 14, wherein the input is a comparator input, the comparator has a comparator output, the transistor is a first transistor having a first current terminal, and the switch mode control circuit includes:
a second transistor having a second current terminal and a third current terminal, the second current terminal coupled to the first current terminal, the comparator input coupled to third current terminal;
a multiplexer coupled to the comparator output;
a first flip-flop coupled to the multiplexer;
a control logic circuit coupled to the first flip-flop; and
a second flip-flop coupled to the first flip-flop, the multiplexer, and the control logic circuit.

### Claim 20 (depends on 19)

The power conversion system of claim 19, wherein the control logic circuit has a control logic circuit input and a control logic circuit output, the multiplexer has a selection input, a first multiplexer input, a second multiplexer input, and a multiplexer output, the first flip-flop has a first flip-flop input, a first clock input, and a first flip-flop output, the second flip-flop has a second flip-flop input, a second clock input, and a second flip-flop output, and wherein:
the first multiplexer input is coupled to the comparator output;
the second multiplexer input is coupled to the second flip-flop output and the control logic circuit input;
the multiplexer output is coupled to the second flip-flop input; and
the first clock input is coupled to the second clock input and the control logic circuit output.

### Claim 21 (depends on 19)

The power conversion system of claim 19, wherein the first transistor has a first gate terminal, the second transistor has a second gate terminal, and the switch mode control circuit includes:
a first logic gate having a first logic gate input, a second logic gate input, and a first logic gate output, the first logic gate input coupled to the first gate terminal, the second logic gate input coupled to a first flip-flop output of the first flip-flop, the first logic gate output coupled to the second gate terminal; and
a second logic gate having a third logic gate input and a second logic gate output, the third logic gate input coupled to the second logic gate input and the first flip-flop output, the second logic gate output coupled to a first flip-flop input of the first flip-flop.

### Claim 22 (depends on 19)

The power conversion system of claim 19, wherein the threshold is a first threshold, the first transistor has a first gate terminal and the second transistor has a second gate terminal, and further including:
a logic gate having a first logic gate input, a second logic gate input, and a logic gate output, the first logic gate input coupled to the first gate terminal, the second logic gate input coupled to a first flip-flop output of the first flip-flop, the logic gate output coupled to the second gate terminal, the logic gate configured to assert a third logic signal in response to a fourth logic signal being asserted and a fifth logic signal being de-asserted, the third logic signal to turn on the second transistor; and wherein
the multiplexer is configured to assert a sixth logic signal in response to the first logic signal being asserted and the first flip-flop asserting the fifth logic signal.

### Claim 23

A method comprising:
in response to a first control signal, sampling an input of a comparator during a first low-side period, the input based on a voltage associated with a transistor coupled to a power converter;
in response to the input satisfying a threshold, asserting a first logic signal;
in response to a second control signal after the first control signal, selecting, with a multiplexer, the first logic signal to be transmitted to a flip-flop during a second low-side period after the first low-side period;
asserting, with the flip-flop, a second logic signal based on the first logic signal; and
adjusting a first operating mode of the power converter to a second operating mode of the power converter in response to the assertion of the second logic signal.

### Claim 24 (depends on 23)

The method of claim 23, wherein the transistor is a first transistor, and further including:
in response to turning on the first transistor during the first low-side period, asserting, with a logic gate coupled to the first transistor, a third logic signal to turn on a second transistor, the second transistor coupled to the first transistor and the logic gate;
in response to the assertion of the third logic signal and the input satisfying the threshold, asserting, with the comparator coupled to the second transistor, the first logic signal;
in response to the assertion of the first logic signal, asserting, with the multiplexer coupled to the comparator, a fourth logic signal to the flip-flop coupled to the multiplexer; and
in response to the second control signal, asserting, with the flip-flop, the second logic signal to a control logic circuit coupled to the flip-flop.

### Claim 25 (depends on 23)

The method of claim 23, wherein the transistor is a first transistor, the power converter includes a second transistor coupled to the first transistor, and further including:
in response to turning on the first transistor during the first low-side period, triggering a sampling window to sample the input;
in response to the second control signal, triggering a hold window to compare the input to the threshold during the second low-side period; and
in response to asserting the first logic signal during the second low-side period, asserting the second logic signal.