# US 2021/0242690 A1 · Semiconductor device and operating method of semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0242690 A1
- Document ID: US20210242690A1
- Status: Published application
- Kind: A1
- Application number: 17/269,330
- Filed: 2019-08-21
- Published: 2021-08-05
- Earliest claimed: 2018-08-31
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Yuki OKAMOTO; Takahiko ISHIZU
- Web page: https://patentgrep.com/patent/US20210242690A1

## CPC

- H02J 7/52: for charge balancing, e.g. equalisation of charge between batteries
- H02J 7/54: Passive balancing, e.g. using resistors or parallel MOSFETs
- H01M 10/425: {Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing (printed circuits H05K1/00)}
- H01M 10/441: {for several batteries or cells simultaneously or sequentially}
- H01M 10/48: Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte (constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569)
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 88/01: {Manufacture or treatment}
- H01M 2010/4271: {Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing}
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 88/00: Three-dimensional [3D] integrated devices
- Y02E 60/10: Energy storage using batteries
- H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H01M: PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

## Abstract

To provide a battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including the battery circuit. The semiconductor device includes n cell-balance circuits (n is an integer greater than or equal to 1). One secondary battery is electrically connected to one cell-balance circuit. The cell-balance circuit includes a comparison circuit, and a memory element is electrically connected to an inverting input terminal of the comparison circuit. The memory element includes a first transistor and a capacitor. A potential is retained. The retained potential changes in accordance with a change in a potential of a negative electrode of the secondary battery. The comparison circuit has a function of comparing the retained potential with a potential of a positive electrode of the secondary battery. Output from the comparison circuit controls a gate voltage of a second transistor electrically connected to the secondary battery in parallel. The first transistor includes a metal oxide including indium in a channel formation region.

## Claims

### Claim 1

A semiconductor device comprising n cell-balance circuits,
wherein n is an integer greater than or equal to 1,
wherein the n cell-balance circuits are electrically connected to n secondary batteries,
wherein one of the n secondary batteries is electrically connected to one of the n cell-balance circuits,
wherein each of the n cell-balance circuits comprises:
a comparison circuit;
a first terminal electrically connected to a non-inverting input terminal of the comparison circuit;
a first transistor one of a source and a drain of which is electrically connected to an inverting input terminal of the comparison circuit;
a first capacitor one electrode of which is electrically connected to the inverting input terminal of the comparison circuit; and
a second terminal electrically connected to the other electrode of the first capacitor,
wherein the first transistor comprises a metal oxide comprising indium in a channel formation region,
wherein the first terminal included in a k-th cell-balance circuit is electrically connected to the second terminal included in a (k−1)th cell-balance circuit,
wherein k is an integer greater than or equal to 3 and less than or equal to n,
wherein the first terminal included in the (k−1)th cell-balance circuit is electrically connected to the second terminal included in a (k−2)th cell-balance circuit, and
wherein a positive electrode of the secondary battery electrically connected to the k-th cell-balance circuit is electrically connected to the first terminal of the k-th cell-balance circuit, and a negative electrode thereof is electrically connected to the second terminal of the k-th cell-balance circuit.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein in the case where a voltage difference between the first terminal and the second terminal included in an m-th cell-balance circuit is larger than a voltage difference between the first terminal and the second terminal included in an (m−1)th cell-balance circuit, a high-potential signal is output from an output terminal of the comparison circuit included in the m-th cell-balance circuit and a low-potential signal is output from an output terminal of the comparison circuit included in the (m−1)th cell-balance circuit, and
wherein m is an integer greater than or equal to 2 and less than or equal to n.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein each of the n cell-balance circuits is configured to supply the sum of a voltage of the second terminal and a voltage A to the inverting input terminal of the comparison circuit, and
wherein the voltage A is greater than or equal to 3 V and less than or equal to 5 V.

### Claim 4

A method of operating a semiconductor device, the semiconductor device comprising a first comparison circuit, a first transistor, a first capacitor, a first terminal, a second terminal, and a third terminal,
wherein the first terminal is electrically connected to a non-inverting input terminal of the first comparison circuit,
wherein one of a source and a drain of the first transistor and one electrode of the first capacitor are electrically connected to an inverting input terminal of the first comparison circuit,
wherein the second terminal is electrically connected to the other electrode of the first capacitor,
wherein the third terminal is electrically connected to the other of the source and the drain of the first transistor,
wherein the first transistor comprises a metal oxide in a channel formation region,
wherein the metal oxide comprises indium,
wherein a positive electrode terminal of a secondary battery is electrically connected to the first terminal,
wherein a negative electrode terminal of the secondary battery is electrically connected to the second terminal,
wherein the method comprises:
a first step of supplying a high-potential signal to a gate of the first transistor,
a second step of supplying a first signal to the third terminal,
a third step of supplying a second signal in accordance with the first signal to the inverting input terminal of the first comparison circuit,
a fourth step of supplying a low-potential signal to a gate of the first transistor,
a fifth step of outputting a low-potential signal from an output terminal of the first comparison circuit, and
a sixth step of reducing a current of the secondary battery by changing a signal from the output terminal of the first comparison circuit from the low-potential signal to the high-potential signal,
wherein the first signal is the sum of a voltage of the second terminal and a voltage A, and
wherein the voltage A is greater than or equal to 3 V and less than or equal to 5 V.

### Claim 5 (depends on 4)

The method of operating a semiconductor device, according to claim 4,
wherein a voltage difference between the first terminal and the second terminal in the fifth step is smaller than a voltage difference between the first terminal and the second terminal in the sixth step.

### Claim 6 (depends on 4)

The method of operating a semiconductor device, according to claim 4, the semiconductor device comprising a second transistor,
wherein the first terminal or the second terminal is electrically connected to one of a source and a drain of the second transistor, and
wherein the output terminal of the first comparison circuit is electrically connected to a gate of the second transistor.

### Claim 7 (depends on 4)

The method of operating a semiconductor device, according to claim 4,
wherein the second signal supplied to the non-inverting input terminal of the first comparison circuit in the third step is retained in the fourth step to the sixth step.

### Claim 8 (depends on 4)

The method of operating a semiconductor device, according to claim 4, the semiconductor device comprising a voltage generation circuit,
wherein the voltage generation circuit comprises a third transistor and a second capacitor,
wherein one electrode of the second capacitor is electrically connected to one of a source and a drain of the third transistor,
wherein the second terminal is electrically connected to the other of the source and the drain of the third transistor,
wherein the voltage generation circuit is configured to generate the first signal, and
wherein the third transistor comprises a metal oxide comprising indium in a channel formation region.

### Claim 9 (depends on 8)

The method of operating a semiconductor device, according to claim 8,
wherein the voltage generation circuit comprises a second comparison circuit,
wherein one of a source and a drain of the third transistor is electrically connected to a non-inverting input terminal of the second comparison circuit,
wherein the third terminal is electrically connected to an inverting input terminal of the second comparison circuit, and
wherein a gate of the first transistor is electrically connected to an output terminal of the second comparison circuit.

### Claim 10

A semiconductor device comprising:
a first comparison circuit;
a second comparison circuit;
a third comparison circuit, a control circuit; and
a secondary battery,
wherein the first comparison circuit, the second comparison circuit, and the third comparison circuit are configured to supply a signal to the control circuit,
wherein the control circuit is configured to control a charge current for the secondary battery in accordance with a signal supplied from the first comparison circuit,
wherein the control circuit is configured to stop charge of the secondary battery in accordance with a signal supplied from the second comparison circuit,
wherein the control circuit is configured to control an upper charge voltage limit of the secondary battery in accordance with a signal supplied from the third comparison circuit,
wherein the first comparison circuit is configured to compare a potential of a positive electrode of the secondary battery with a first reference potential,
wherein the second comparison circuit is configured to compare the potential of the positive electrode of the secondary battery with a second reference potential, and
wherein the third comparison circuit is configured to compare an ambient temperature with a third reference potential.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10,
wherein a source or a drain of a first transistor is electrically connected to a non-inverting input terminal or an inverting input terminal of the first comparison circuit,
wherein a source or a drain of a second transistor is electrically connected to a non-inverting input terminal or an inverting input terminal of the second comparison circuit,
wherein a source or a drain of a third transistor is electrically connected to a non-inverting input terminal or an inverting input terminal of the third comparison circuit, and
a channel formation region of each of the first transistor, the second transistor, and the third transistor comprises a metal oxide comprising indium.