# US 2021/0242595 A1 · Chip radio frequency package and radio frequency module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242595 A1 - Document ID: US20210242595A1 - Status: Published application - Kind: A1 - Application number: 16/891,265 - Filed: 2020-06-03 - Published: 2021-08-05 - Earliest claimed: 2020-02-05 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Applicants: Samsung Electro-Mechanics Co., Ltd. - Inventors: Hak Gu KIM; Ho Kyung KANG; Seong Jong CHEON; Young Sik HUR; Jin Seon PARK; Yong Duk LEE - Web page: https://patentgrep.com/patent/US20210242595A1 ## CPC - H01Q 9/0414: {in a stacked or folded configuration} - H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package} - H01Q 1/38: formed by a conductive layer on an insulating support {(patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142)} - H01Q 5/35: using two or more simultaneously fed points - H01Q 21/08: the units being spaced along or adjacent to a rectilinear path {(waveguide fed H01Q21/0037)} - H01Q 9/0407: {Substantially flat resonant element parallel to ground plane, e.g. patch antenna (dipole H01Q9/285; monopole H01Q9/40)} - H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72) ## Abstract A chip radio frequency package includes a substrate including a first cavity, first and second connection members, a core member, a radio frequency integrated circuit (RFIC) disposed on an upper surface of the substrate, and a first front-end integrated circuit (FEIC) disposed in the first cavity. The core member includes a core insulating layer and a core via that penetrates the core insulating layer. The first connection member has a structure in which a first insulating layer and a first wiring layer are stacked. The second connection member has a second structure in which a second insulating layer and a second wiring layer are stacked. The RFIC inputs or outputs a base signal and a first radio frequency (RF) signal having a frequency higher than a frequency of the base signal, and the first FEIC inputs or outputs the first RF signal and a second RF signal. ## Claims ### Claim 1 A chip radio frequency package, comprising: a substrate including a first cavity, a first connection member and a second connection member, and including a core member disposed between the first connection member and the second connection member; a radio frequency integrated circuit (RFIC) disposed on an upper surface of the substrate; and a first front-end integrated circuit (FEIC) disposed in the first cavity, wherein the core member comprises a core insulating layer and a core via disposed to penetrate the core insulating layer, the first connection member has a first stacked structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked, and the first wiring layer is electrically connected to the core via, the second connection member has a second stacked structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked, and the second wiring layer is electrically connected to the core via, the RFIC is configured to input or output a base signal and a first radio frequency (RF) signal which has a frequency higher than a frequency of the base signal, through the at least one second wiring layer, and the first FEIC is configured to input or output the first RF signal and a second RF signal which has a power different from a power of the first RF signal. ### Claim 2 (depends on 1) The chip radio frequency package of claim 1, wherein the first connection member is disposed on a lower surface of the core member, and the second connection member is disposed on an upper surface of the core member. ### Claim 3 (depends on 1) The chip radio frequency package of claim 1, further comprising a third connection member having a third stacked structure in which at least one third insulating layer and at least one third wiring layer are alternately stacked, and the third connection member is disposed on a lower surface of the first connection member, wherein the first FEIC is disposed on an upper surface of the third connection member. ### Claim 4 (depends on 3) The chip radio frequency package of claim 3, wherein the first FEIC is configured to input or output the first and second RF signals in a downward direction. ### Claim 5 (depends on 3) The chip radio frequency package of claim 3, wherein the first connection member is disposed below the core member, the second connection member is disposed above the core member, and the third connection member is disposed below the core member. ### Claim 6 (depends on 1) The chip radio frequency package of claim 1, wherein the first connection member is disposed below the core member, and the second connection member is disposed above the core member. ### Claim 7 (depends on 6) The chip radio frequency package of claim 6, wherein the first FEIC is surrounded by the core member and the first connection member, and is disposed on a lower surface of the second connection member. ### Claim 8 (depends on 1) The chip radio frequency package of claim 1, wherein a horizontal width of a portion corresponding to an upper surface of the core member in the first cavity is less than a horizontal width of a portion corresponding to a lower surface of the core member. ### Claim 9 (depends on 1) The chip radio frequency package of claim 1, wherein the substrate further comprises a cavity cover layer in which at least a portion thereof is disposed on an upper surface of the first cavity, and the cavity cover layer is surrounded by one or more of the core member and the second connection member. ### Claim 10 (depends on 9) The chip radio frequency package of claim 9, wherein the cavity cover layer is electrically connected to the RFIC. ### Claim 11 (depends on 9) The chip radio frequency package of claim 9, further comprising a second FEIC disposed in a second cavity of the substrate, wherein a portion of the cavity cover layer is disposed on an upper surface of the second cavity. ### Claim 12 (depends on 1) The chip radio frequency package of claim 1, further comprising a second FEIC disposed in a second cavity of the core member. ### Claim 13 (depends on 12) The chip radio frequency package of claim 12, wherein the first cavity and the second cavity are spaced apart from each other, and respective side surfaces of the first cavity and the second cavity are inclined. ### Claim 14 (depends on 12) The chip radio frequency package of claim 12, wherein the second FEIC is configured to input or output a third RF signal and a fourth RF signal, wherein the fourth RF signal has a power that is different from a power of the third RF signal, and frequencies of the third RF signal and the fourth RF signal are different from frequencies of the first RF signal and the second RF signal. ### Claim 15 (depends on 12) The chip radio frequency package of claim 12, wherein the second FEIC is configured to receive a third RF signal, amplify the third RF signal, and output a fourth RF signal, the first FEIC is configured to amplify the first RF signal, and output the second RF signal, and the RFIC is configured to convert a base signal into the first RF signal, and convert the fourth RF signal into a base signal. ### Claim 16 (depends on 12) The chip radio frequency package of claim 12, wherein at least a portion of at least one of the first FEIC and the second FEIC overlaps the RFIC in a vertical direction. ### Claim 17 A radio frequency module, comprising: a first substrate including a first cavity, a first connection member and a second connection member, and including a core member disposed between the first connection member and the second connection members; a radio frequency integrated circuit (RFIC) disposed on an upper surface of the first substrate; a first front-end integrated circuit (FEIC) disposed in the first cavity; a second substrate having an upper surface on which the first substrate is disposed; and an electrical connection structure configured to form an electrical connection between the second substrate and the first substrate, wherein the core member comprises a core insulating layer and a core via disposed to penetrate the core insulating layer, the first connection member has a first stacked structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked, and the at least one first wiring layer is electrically connected to the core via, the second connection member has a second stacked structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked, and the at least one second wiring layer is electrically connected to the core via, the RFIC is configured to input or output a base signal and a first radio frequency (RF) signal which has a frequency higher than a frequency of the base signal, through the at least one second wiring layer, and the first FEIC is configured to input or output the first RF signal and a second RF signal, which has a power different from a power of the first RF signal, to the second substrate. ### Claim 18 (depends on 17) The radio frequency module of claim 17, wherein the first connection member is disposed on a lower surface of the core member, and the second connection member is disposed on an upper surface of the core member. ### Claim 19 (depends on 17) The radio frequency module of claim 17, wherein the second substrate comprises a patch antenna pattern configured to transmit or receive the first RF signal or the second RF signal; and a feed via connected to the patch antenna pattern. ### Claim 20 (depends on 17) The radio frequency module of claim 17, further comprising a second FEIC disposed in a second cavity of the core member. ### Claim 21 (depends on 17) The radio frequency module of claim 17, further comprising an encapsulant that encapsulates at least a portion of the RFIC on an upper surface of the first substrate. ### Claim 22 (depends on 17) The radio frequency module of claim 17, wherein a lower surface of the first substrate is smaller than an upper surface of the second substrate.