# US 2021/0242401 A1 · Memory device and programming method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242401 A1 - Document ID: US20210242401A1 - Status: Published application - Kind: A1 - Application number: 16/919,071 - Filed: 2020-07-01 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Chao-I Wu - Web page: https://patentgrep.com/patent/US20210242401A1 ## CPC - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10N 70/8613: {Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0069: {Writing or programming circuits or methods} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8413: {adapted for resistive heating} - H10N 70/8828: {Tellurides, e.g. GeSbTe} - G11C 13/0061: {Timing circuits or methods} - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device and a programming method of the memory device are provided. The memory device includes a bottom electrode, a heater, a phase change layer and a top electrode. The heater is disposed on the bottom electrode, and includes heat conducting materials different from one another in terms of electrical resistivity. A first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion. A second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials. The phase change layer is disposed on the heater and in contact with the heat conducting materials. The top electrode is disposed on the phase change layer. ## Claims ### Claim 1 A memory device, comprising: a bottom electrode; a heater, disposed on the bottom electrode and comprising heat conducting materials, wherein electrical resistivities of the heat conducting materials are different from one another, a first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion, a second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials; a phase change layer, disposed on the heater and in contact with the heat conducting materials; and a top electrode, disposed on the phase change layer. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein the first one of the conducting materials is formed as a cup shape structure with a recess inside the cup shape structure, and the second one of the conducting materials is disposed in the recess. ### Claim 3 (depends on 1) The memory device according to claim 1, wherein top surfaces of the heat conducting materials collectively define at least a portion of a top surface of the heater. ### Claim 4 (depends on 1) The memory device according to claim 1, wherein the heat conducting materials are made of the same combination of elements, and have different elemental percentages. ### Claim 5 (depends on 4) The memory device according to claim 4, wherein the heat conducting materials are made of titanium nitride, and have different titanium atomic percentages. ### Claim 6 (depends on 1) The memory device according to claim 1, wherein the heater further comprises a heat isolation layer covering an outermost sidewall and a bottommost surface of the heat conducting materials. ### Claim 7 (depends on 6) The memory device according to claim 6, wherein the heat isolation layer is less thermally conductive than the heat conducting materials. ### Claim 8 (depends on 6) The memory device according to claim 6, wherein a top surface of the heat isolation layer and top surfaces of the heat conducting materials collectively define a top surface of the heater. ### Claim 9 (depends on 1) The memory device according to claim 1, wherein the second one of the heat conducting materials covers an inner surface of the first one of the heat conducting materials, a third one of the heat conducting materials covers an inner surface of the second one of the heat conducting materials, and is formed in a pillar shape. ### Claim 10 (depends on 9) The memory device according to claim 9, wherein a first electrical resistivity of the first one of the heat conducting material is less than a second resistivity of the second one of the heat conducting materials, and the second resistivity is less than a third resistivity of the third one of the heat conducting materials. ### Claim 11 (depends on 9) The memory device according to claim 9, wherein top view patterns of the heat conducting materials are concentric patterns. ### Claim 12 (depends on 1) The memory device according to claim 1, wherein the heater has a footprint area smaller than a footprint area of the phase change layer, and smaller than a footprint area of the bottom electrode. ### Claim 13 A memory device, comprising: a bottom electrode; a heater, disposed on the bottom electrode and having heat conducting regions configured to simultaneously produce different amounts of joule heat, wherein metallic element percentages of the heat conducting regions are different from one another; a phase change layer, disposed on the heater and in contact with top ends of the heat conducting regions; and a top electrode, disposed on the phase change layer. ### Claim 14 (depends on 13) The memory device according to claim 13, wherein an electrical resistivity of the heater decreases outwardly from a center of the heater. ### Claim 15 (depends on 13) The memory device according to claim 13, wherein one of the heat conducting regions is laterally surrounded by another one of the heat conducting regions. ### Claim 16 A programming method of a memory device, wherein the memory device comprises a bottom electrode, a heater disposed on the bottom electrode and having heat conducting materials different from one another in terms of electrical resistivity, and a phase change layer disposed on the heater and having active regions respectively in contact with one of the heat conducting materials of the heater, and the programming method of the memory device comprises: providing a first current pulse to the heater, so as to subject all of the active regions for phase transition; and providing a second current pulse to the heater, so as to select a portion of the active regions for phase transition. ### Claim 17 (depends on 16) The programming method of the memory device according to claim 16, wherein the first current pulse has a first amplitude and a first duration time, the second current pulse has a second amplitude and a second duration time, the first amplitude is greater than the second amplitude, and the first duration times is shorter than the second duration time. ### Claim 18 (depends on 17) The programming method of the memory device according to claim 17, wherein the second current pulse has a stepwise descending edge, and the first current pulse has an abrupt descending edge. ### Claim 19 (depends on 16) The programming method of the memory device according to claim 16, wherein the first current pulse has a first amplitude and a first duration time, the second current pulse has a second amplitude and a second duration time, the first amplitude is greater than the second amplitude, and the first amplitude is less than the second amplitude. ### Claim 20 (depends on 19) The programming method of the memory device according to claim 19, wherein the first and second current pulses respectively have a stepwise descending edge.