# US 2021/0242399 A1 · Top electrode via with low contact resistance

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- Number: US 2021/0242399 A1
- Document ID: US20210242399A1
- Status: Published application
- Kind: A1
- Application number: 16/921,133
- Filed: 2020-07-06
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Bi-Shen Lee; Hai-Dang Trinh; Hsun-Chung Kuang; Tzu-Chung Tsai; Yao-Wen Chang
- Web page: https://patentgrep.com/patent/US20210242399A1

## CPC

- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/841: {Electrodes}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/883: {Oxides or nitrides}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

## Claims

### Claim 1

A memory device, comprising:
a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate;
a data storage structure disposed over the bottom electrode;
a first top electrode layer disposed over the data storage structure;
a second top electrode layer on the first top electrode layer, wherein the second top electrode layer is less susceptible to oxidation than the first top electrode layer; and
a top electrode via over and electrically coupled to the second top electrode layer.

### Claim 2 (depends on 1)

The memory device of claim 1,
wherein the top electrode via extends from over a top surface of the second top electrode layer to below the top surface of the second top electrode layer; and
wherein the top electrode via is separated from the first top electrode layer by the second top electrode layer.

### Claim 3 (depends on 1)

The memory device of claim 1, further comprising:
a top electrode oxide disposed between the top electrode via and the second top electrode layer.

### Claim 4 (depends on 3)

The memory device of claim 3, further comprising:
a first oxide disposed along one or more sidewalls of the first top electrode layer, wherein the first oxide has a greater thickness than the top electrode oxide.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the second top electrode layer comprises titanium nitride, ruthenium, tungsten, tin, zirconium, aluminum nitride, silver, strontium, thallium, vanadium, zirconium nitride, or hafnium nitride.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the first top electrode layer comprises tantalum and the second top electrode layer comprises titanium nitride.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the second top electrode layer has a thickness in a range of between approximately 20 Angstroms (Å) and approximately 300 Å.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the second top electrode layer has a corrosion potential of greater than or equal to approximately −0.4V.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the second top electrode layer has a boiling point in a fluorine gas of greater than approximately 1500° C.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the second top electrode layer comprises a material that utilizes a Gibbs free energy of greater than −600 kJ/mol to form an oxide.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the second top electrode layer has a first non-zero thickness directly below the top electrode via and a second thickness outside of the top electrode via, the second thickness greater than the first non-zero thickness.

### Claim 12

An integrated chip, comprising:
a memory device disposed over a substrate, the memory device comprising a data storage structure disposed between a bottom electrode and a multi-layer top electrode;
a top electrode via disposed over and electrically coupled to the multi-layer top electrode;
wherein the multi-layer top electrode comprises a first top electrode layer disposed over the data storage structure, and a second top electrode layer on the first top electrode layer and comprising a different material than the first top electrode layer; and
wherein the second top electrode layer has a larger corrosion potential than the first top electrode layer.

### Claim 13 (depends on 12)

The integrated chip of claim 12, further comprising:
a hard mask layer disposed over the second top electrode layer and having a first thickness, wherein the top electrode via extends through the hard mask layer to a first bottom surface that is between sidewalls of the second top electrode layer and that is separated from the first top electrode layer by the second top electrode layer.

### Claim 14 (depends on 13)

The integrated chip of claim 13, further comprising:
a second memory device disposed over the substrate and comprising a second data storage structure disposed between a second bottom electrode and a second multi-layer top electrode, wherein the second multi-layer top electrode comprises a fourth top electrode layer that is separated from the second data storage structure by a third top electrode layer that has a smaller corrosion potential than the fourth top electrode layer;
a second top electrode via disposed over and electrically coupled to the second multi-layer top electrode; and
a second hard mask layer disposed over the fourth top electrode layer and having a second thickness that is larger than the first thickness, wherein the second top electrode via extends through the second hard mask layer to a second bottom surface that is separated from the third top electrode layer by the fourth top electrode layer.

### Claim 15

A method of forming a memory device, comprising:
forming a data storage layer on a bottom electrode layer over a substrate;
forming a first top electrode layer over the data storage layer and a second top electrode layer over the first top electrode layer, wherein the first top electrode layer has a smaller corrosion potential than the second top electrode layer;
performing a first patterning process on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode; and
performing a second patterning process on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming an upper inter-level dielectric (ILD) layer over the multi-layer top electrode;
etching the upper ILD layer to form a top electrode via hole extending to the second top electrode layer; and
forming a top electrode via within the top electrode via hole.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
etching the upper ILD layer using an etchant comprising a fluorine gas.

### Claim 18 (depends on 15)

The method of claim 15, wherein the second top electrode layer has a corrosion potential of greater than or equal to approximately −0.4V.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first top electrode layer has a greater thickness than the second top electrode layer.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
exposing the first top electrode layer and the second top electrode layer to an ambient environment, wherein the ambient environment forms a first oxide along sides of the first top electrode layer and a second oxide along sides of the second top electrode layer; and
wherein the first oxide has a greater thickness than the second oxide.