# US 2021/0242398 A1 · Intercalated metal/dielectric structure for nonvolatile memory devices

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- Number: US 2021/0242398 A1
- Document ID: US20210242398A1
- Status: Published application
- Kind: A1
- Application number: 17/218,324
- Filed: 2021-03-31
- Published: 2021-08-05
- Earliest claimed: 2018-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Mauricio Manfrini; Chung-Te Lin; Gerben Doornbos; Marcus Johannes Henricus van Dal
- Web page: https://patentgrep.com/patent/US20210242398A1

## CPC

- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- H10B 63/22: {of the metal-insulator-metal type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

## Claims

### Claim 1

An integrated chip including a memory device, the memory device comprising:
a bottom electrode disposed over a semiconductor substrate;
an upper electrode disposed over the bottom electrode; and
an intercalated metal/dielectric structure sandwiched between the bottom electrode and the upper electrode, the intercalated metal/dielectric structure comprising a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer; and
wherein at least one of the upper electrode and the bottom electrode have a first width and at least one of the lower dielectric layer and the upper dielectric layer have a second width that is different from the first width.

### Claim 2 (depends on 1)

The integrated chip of claim 1, wherein when the memory device is in a first state, a lower conductive filament extends from the bottom electrode through the lower dielectric layer and to the first metal layer, and an upper conductive filament extends from the first metal layer through the upper dielectric layer and to the upper electrode.

### Claim 3 (depends on 2)

The integrated chip of claim 2, wherein when the memory device is in a second state, at least a portion of the lower conductive filament is removed or broken so the lower dielectric layer separates the bottom electrode from the first metal layer, and/or at least a portion of the upper conductive filament is removed or broken so the upper dielectric layer separates the first metal layer from the upper electrode.

### Claim 4 (depends on 1)

The integrated chip of claim 1, wherein the intercalated metal/dielectric structure further comprises:
a second metal layer disposed over the upper dielectric layer, the second metal layer separating the upper dielectric layer from the upper electrode.

### Claim 5 (depends on 1)

The integrated chip of claim 1, wherein the intercalated metal/dielectric structure further comprises:
a second metal layer disposed over the bottom electrode, the second metal layer separating the bottom electrode from the lower dielectric layer.

### Claim 6 (depends on 5)

The integrated chip of claim 5, wherein the intercalated metal/dielectric structure further comprises:
a third metal layer disposed over the upper dielectric layer, the third metal layer separating the upper dielectric layer from the upper electrode.

### Claim 7 (depends on 6)

The integrated chip of claim 6, wherein the upper dielectric layer and the lower dielectric layer comprise a high-k dielectric material; the first metal layer, the second metal layer, and the third metal layer comprise copper, aluminum, or tungsten; and the upper electrode and the bottom electrode comprise tantalum or titanium.

### Claim 8 (depends on 1)

The integrated chip of claim 1, further comprising a resistive random access memory (RRAM) cell disposed over the upper electrode, the RRAM cell comprising:
a data storage dielectric layer disposed over the upper electrode; and
a top electrode disposed over the data storage dielectric layer.

### Claim 9 (depends on 1)

The integrated chip of claim 1, further comprising:
a dielectric liner along sidewalls of the intercalated metal/dielectric structure.

### Claim 10

An integrated chip, comprising:
an interconnect structure including a lower metal layer and an upper metal layer which are separated from one another by a first inter-level dielectric (ILD) layer;
a bottom electrode disposed over the lower metal layer;
a top electrode disposed over the bottom electrode, the top electrode residing below the upper metal layer;
a plurality of metal layers and a plurality of dielectric layers stacked in alternating fashion over one another and sandwiched between the top electrode and the bottom electrode;
an interlayer dielectric along outer sidewalls of the top electrode and along outer sidewalls of the plurality of metal layers and the plurality of dielectric layers; and
a dielectric liner separating the outer sidewalls of the top electrode from the interlayer dielectric and extending continuously downward along outer sidewalls of the plurality of metal layers and the plurality of dielectric layers to separate the outer sidewalls of the plurality of metal layers and the plurality of dielectric layers from the interlayer dielectric.

### Claim 11 (depends on 10)

The integrated chip of claim 10, wherein at least two of the plurality of metal layers have different thicknesses from one another.

### Claim 12 (depends on 10)

The integrated chip of claim 10, wherein at least two of the plurality of dielectric layers have different thicknesses from one another.

### Claim 13 (depends on 10)

The integrated chip of claim 10, wherein a maximum thickness of any of the plurality of dielectric layers is less than 10 nm.

### Claim 14 (depends on 10)

The integrated chip of claim 10, wherein the plurality of dielectric layers include a plurality of conductive filaments, respectively, wherein each conductive filament extends through a corresponding dielectric layer to couple neighboring metal layers in the plurality of metal layers to one another.

### Claim 15

An integrated chip, comprising:
a lower interconnect structure within a first inter-level dielectric (ILD) layer over a substrate;
a bottom electrode disposed over the lower interconnect structure;
an upper electrode disposed over the bottom electrode; and
an intercalated metal/dielectric structure sandwiched between the bottom electrode and the upper electrode, the intercalated metal/dielectric structure comprising a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

### Claim 16 (depends on 15)

The integrated chip of claim 15, further comprising:
a memory element over the upper electrode; and
a top electrode over the memory element.

### Claim 17 (depends on 16)

The integrated chip of claim 16, further comprising:
a second ILD layer over the top electrode; and
a via and top metal line within the second ILD layer, wherein the via couples the top metal line to an upper portion of the upper electrode.

### Claim 18 (depends on 15)

The integrated chip of claim 15, wherein the intercalated metal/dielectric structure includes five or fewer dielectric layers between the lower interconnect structure and the upper electrode.

### Claim 19 (depends on 15)

The integrated chip of claim 15, further comprising:
circuitry configured to apply a first bias between the lower interconnect structure and the upper electrode to induce a first state in the intercalated metal/dielectric structure; wherein in the first state, a lower conductive filament extends from the lower interconnect structure through the lower dielectric layer and to the first metal layer, and an upper conductive filament extends from the first metal layer through the upper dielectric layer and to the upper electrode.

### Claim 20 (depends on 19)

The integrated chip of claim 19, wherein the circuitry is further configured to apply a second bias between the lower interconnect structure and the upper electrode to induce a second state in the intercalated metal/dielectric structure; wherein in the second state, at least a portion of the lower conductive filament is removed or broken so the lower dielectric layer separates the lower interconnect structure from the first metal layer, and/or at least a portion of the upper conductive filament is removed or broken so the upper dielectric layer separates the first metal layer from the upper electrode.