# US 2021/0242349 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242349 A1 - Document ID: US20210242349A1 - Status: Published application - Kind: A1 - Application number: 17/240,616 - Filed: 2021-04-26 - Published: 2021-08-05 - Earliest claimed: 2018-07-20 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: SOONMOON JUNG; DAEWON HA; SUNGMIN KIM; HYOJIN KIM; KEUN HWI CHO - Web page: https://patentgrep.com/patent/US20210242349A1 ## CPC - H10D 30/6733: {Multi-gate TFTs} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)} - H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)} - H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon} - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate having a plurality of first active patterns, a plurality of second active patterns, a plurality of third active patterns, and a plurality of fourth active patterns, the plurality of first active patterns being located in a PMOSFET section of a logic cell region of the semiconductor device, the plurality of second active patterns being located in an NMOSFET section of the logic cell region, the plurality of third active patterns in a memory cell region of the semiconductor device, the plurality of fourth active patterns being located in between respective ones of the third active patterns, each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other, a plurality of first source/drain patterns, a plurality of second source/drain patterns, a plurality of third source/drain patterns, and a plurality of fourth source/drain patterns on the first to fourth active patterns, respectively; and a first active contact, a second active contact, a third active contact, and a fourth active contact connected to the first to fourth source/drain patterns, respectively; wherein the distance between the first and second active contacts is larger than the distance between the third and fourth active contacts. ### Claim 2 (depends on 1) The device of claim 1, wherein the second and third source/drain patterns are n-type impurity regions, and the third and fourth source/drain patterns are p-type impurity regions. ### Claim 3 (depends on 1) The device of claim 1, further comprising a first gate electrode that runs across the first and second active patterns, and a second gate electrode that runs across the third and fourth active patterns; and a device isolation layer on the substrate defining the first to fourth active patterns; wherein the device isolation layer includes first segments disposed beneath the first and second source/drain patterns, second segments disposed beneath the first gate electrode, third segments disposed beneath the third and fourth source/drain patterns, and fourth segments disposed beneath the second gate electrode, and wherein a level of uppermost portions of top surfaces of the first segments is higher than a level of uppermost portions of top surfaces of the third segments. ### Claim 4 (depends on 1) The device of claim 1, further comprising a first gate electrode that runs across the first and second active patterns, and a second gate electrode that runs across the third and fourth active patterns; and a gate contact coupled with the second gate electrode, and spaced apart from the first gate electrode. ### Claim 5 (depends on 4) The device of claim 4, further comprising a gate dielectric pattern interposed between the second gate electrode and the first and second semiconductor patterns, wherein the gate dielectric pattern surrounds the first and second semiconductor patterns. ### Claim 6 (depends on 1) The device of claim 1, wherein each of the third and fourth active patterns further includes third and fourth semiconductor patterns, the first, second, third and fourth semiconductor patterns of each of the third and fourth active patterns being vertically spaced apart from each other. ### Claim 7 (depends on 1) The device of claim 1, further comprising a device isolation layer disposed in a plurality of logic region trenches and a plurality of memory cell region trenches, wherein the logic region trenches being located between adjacent ones of the first active patterns and between adjacent ones of the second active patterns, respectively, wherein the memory cell region trenches being located between adjacent ones of the fourth active patterns and between said respective ones of the third active patterns and the fourth active patterns adjacent thereto, respectively, and wherein the memory cell region trenches are deeper than the logic region trenches. ### Claim 8 (depends on 1) The device of claim 1, wherein the first and second semiconductor patterns connect the third source/drain patterns to each other, and connect the fourth source/drain patterns to each other. ### Claim 9 A semiconductor device, comprising: a substrate having a plurality of first active patterns, a plurality of second active patterns, a plurality of third active patterns, and a plurality of fourth active patterns, the plurality of first active patterns being located in a PMOSFET section of a first region of the semiconductor device, the plurality of second active patterns being located in an NMOSFET section of the first region, the plurality of third active patterns being located in a second region of the semiconductor device, the plurality of fourth active patterns being located in between respective ones of the third active patterns, each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other; a device isolation layer on the substrate defining the first to fourth active patterns; a first gate electrode provided in the first region that runs across the first and second active patterns, and a second gate electrode provided in the second region that runs across the third and fourth active patterns; and a gate contact provided on the second gate electrode, wherein the gate contact is coupled with the second gate electrode, and spaced apart from the first gate electrode. ### Claim 10 (depends on 9) The device of claim 9, further comprising a plurality of first source/drain patterns, a plurality of second source/drain patterns, a plurality of third source/drain patterns, and a plurality of fourth source/drain patterns on the first to fourth active patterns, respectively, and wherein the second and third source/drain patterns are n-type impurity regions, and the first and fourth source/drain patterns are p-type impurity regions. ### Claim 11 (depends on 10) The device of claim 10, wherein the device isolation layer includes first segments disposed beneath the first and second source/drain patterns, second segments disposed beneath the first gate electrode, third segments disposed beneath the third and fourth source/drain patterns, and fourth segments disposed beneath the second gate electrode, and wherein a level of uppermost portions of top surfaces of the first segments is higher than a level of uppermost portions of top surfaces of the third segments. ### Claim 12 (depends on 11) The device of claim 11, wherein a level of uppermost portions of top surfaces of the second segments is higher than a level of uppermost portions of top surfaces of the fourth segments. ### Claim 13 (depends on 10) The device of claim 10, further comprising a first active contact, a second active contact, a third active contact, and a fourth active contact connected to the first to fourth source/drain patterns, respectively; wherein the distance between the first and second active contacts is larger than the distance between the third and fourth active contacts. ### Claim 14 (depends on 9) The device of claim 9, further comprising a gate dielectric pattern interposed between the second gate electrode and the first and second semiconductor patterns, wherein the gate dielectric pattern surrounds the first and second semiconductor patterns. ### Claim 15 (depends on 9) The device of claim 9, wherein the device isolation layer disposed in a plurality of logic region trenches and a plurality of memory cell region trenches, wherein the logic region trenches being located between adjacent ones of the first active patterns and between adjacent ones of the second active patterns, respectively, wherein the memory cell region trenches being located between adjacent ones of the fourth active patterns and between said respective ones of the third active patterns and the fourth active patterns adjacent thereto, respectively, and wherein the memory cell region trenches are deeper than the logic region trenches. ### Claim 16 A semiconductor device, comprising: a substrate having a plurality of first active patterns, a plurality of second active patterns, a plurality of third active patterns, and a plurality of fourth active patterns, the plurality of first active patterns being located in a PMOSFET section of a first region of the semiconductor device, the plurality of second active patterns being located in an NMOSFET section of the first region, the plurality of third active patterns being located in a second region of the semiconductor device, and the plurality of fourth active patterns being located in between respective ones of the third active patterns, each of the third and fourth active patterns includes first, second, third, and fourth semiconductor patterns that are vertically spaced apart from each other, a first gate electrode provided on the first region that runs across the first and second active patterns, and a second gate electrode provided on the second region that runs across the third and fourth active patterns; and a gate dielectric pattern interposed between the second gate electrode and the first to fourth semiconductor patterns, wherein the gate dielectric pattern surrounds the first to fourth semiconductor patterns. ### Claim 17 (depends on 16) The device of claim 16, wherein the substrate defining a plurality of first trenches and a plurality of second trenches, the first trenches being located between adjacent ones of the first active patterns and between adjacent ones of the second active patterns, respectively, and the second trenches being located between adjacent ones of the fourth active patterns and between said respective ones of the third active patterns and the fourth active patterns adjacent thereto, respectively; and wherein a device isolation layer disposed in the plurality of first trenches and in the plurality of second trenches. ### Claim 18 (depends on 17) The device of claim 17, wherein the first trenches and the second trenches extend to substantially the same depths in the substrate. ### Claim 19 (depends on 17) The device of claim 17, further comprising: a third trench disposed between the first and second active patterns, wherein the third trench is deeper than each of the first and second trenches. ### Claim 20 (depends on 16) The device of claim 16, further comprising: gate electrodes that each run across the first to fourth semiconductor patterns, and a dielectric pattern between the gate electrodes.