# US 2021/0242347 A1 · Multi-gate transistor and memory device using the same

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- Number: US 2021/0242347 A1
- Document ID: US20210242347A1
- Status: Published application
- Kind: A1
- Application number: 16/877,518
- Filed: 2020-05-19
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Cheng-Lin SUNG; Pei-Ying DU; Hang-Ting LUE
- Web page: https://patentgrep.com/patent/US20210242347A1

## CPC

- H10D 30/687: {having more than two programming levels}
- G11C 11/5621: {using charge storage in a floating gate}
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10D 30/6733: {Multi-gate TFTs}
- H10D 30/691: {having more than two programming levels}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A multi-gate transistor includes; a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.

## Claims

### Claim 1

A multi-gate transistor including:
a doped drain region;
a doped source region;
a gate group including a first gate and a second gate;
a channel, the doped drain region and the doped source region being on respective two sides of the channel; and
an interlayer, formed between the channel and the gate group,
wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.

### Claim 2 (depends on 1)

The multi-gate transistor according to claim 1, wherein
when the first gate voltage is higher than a threshold voltage, a first sub-channel corresponding to the first gate is induced as an N sub-channel in the channel; and
when the second gate voltage is lower than the threshold voltage, a second sub-channel corresponding to the second gate is induced as a P sub-channel in the channel.

### Claim 3 (depends on 1)

The multi-gate transistor according to claim 1, wherein the gate group further includes a third gate,
when the first gate voltage is lower than a threshold voltage, a first sub-channel corresponding to the first gate is induced as a P sub-channel in the channel;
when the second gate voltage is higher than the threshold voltage, a second sub-channel corresponding to the second gate is induced as an N sub-channel in the channel; and
when a third gate voltage applied to the third gate is higher than the threshold voltage, a third sub-channel corresponding to the third gate is induced as an N sub-channel in the channel.

### Claim 4 (depends on 1)

The multi-gate transistor according to claim 1, wherein the gate group further includes a third gate,
when the first gate voltage is lower than a threshold voltage, a first sub-channel corresponding to the first gate is induced as a P sub-channel in the channel;
when the second gate voltage is lower than the threshold voltage, a second sub-channel corresponding to the second gate is induced as a P sub-channel in the channel; and
when a third gate voltage applied to the third gate is higher than the threshold voltage, a third sub-channel corresponding to the third gate is induced as an N sub-channel in the channel.

### Claim 5 (depends on 1)

The multi-gate transistor according to claim 1, wherein the gate group further includes a third gate,
when the first gate voltage is higher than a threshold voltage, a first sub-channel corresponding to the first gate is induced as an N sub-channel in the channel;
when the second gate voltage is lower than the threshold voltage, a second sub-channel corresponding to the second gate is induced as a P sub-channel in the channel; and
when a third gate voltage applied to the third gate is higher than the threshold voltage, a third sub-channel corresponding to the third gate is induced as an N sub-channel in the channel.

### Claim 6 (depends on 1)

The multi-gate transistor according to claim 1, wherein the gate group further includes a third gate,
when the first gate voltage is higher than a threshold voltage, a first sub-channel corresponding to the first gate is induced as an N sub-channel in the channel;
when the second gate voltage is lower than the threshold voltage, a second sub-channel corresponding to the second gate is induced as a P sub-channel in the channel; and
when a third gate voltage applied to the third gate is lower than the threshold voltage, a third sub-channel corresponding to the third gate is induced as a P sub-channel in the channel.

### Claim 7 (depends on 1)

The multi-gate transistor according to claim 1, wherein the interlayer is a gate oxide layer or a charge storage layer, and the charge storage layer is a floating gate or a charge trapping structure.

### Claim 8 (depends on 1)

A memory device including:
a memory array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines;
a data transporting circuit coupled to the memory array;
an integrate-and-fire circuit coupled to the data transporting circuit, the data transporting circuit transporting a plurality of operations results of the memory cells of the memory array to the integrate-and-fire circuit, the integrate-and-fire circuit outputting a plurality of pluses according to the operations results of the memory cells of the memory array, wherein a count of the pulses represents the operations results of the memory cells; and
a control circuit coupled to the integrate-and-fire circuit and the memory array, the control circuit outputting a control signal to the integrate-and-fire circuit and the memory array based on the pulses from the integrate-and-fire circuit,
wherein the integrate-and-fire circuit includes a multi-gate transistor as claimed in claim 1.

### Claim 9

A multi-gate transistor including:
a doped drain region;
a doped source region;
a gate group including a first gate and a second gate;
a doped channel, the doped drain region and the doped source region being on respective two sides of the doped channel; and
an interlayer, formed between the doped channel and the gate group,
wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group to enhance channel sensing of the doped channel and the multi-gate transistor equivalently behaves as a PNPN structure.