# US 2021/0242344 A1 · Transistors with a hybrid source or drain

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- Number: US 2021/0242344 A1
- Document ID: US20210242344A1
- Status: Published application
- Kind: A1
- Application number: 16/781,236
- Filed: 2020-02-04
- Published: 2021-08-05
- Earliest claimed: 2020-02-04
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GLOBALFOUNDRIES U.S. Inc.
- Inventors: Haiting Wang; Sipeng Gu; Jiehui Shu; Baofu Zhu
- Web page: https://patentgrep.com/patent/US20210242344A1

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.

## Claims

### Claim 1

A structure for a field-effect transistor, the structure comprising:
a semiconductor fin including a cavity;
a first gate structure that extends over the semiconductor fin, the first gate structure having a first side surface and a second side surface opposite the first side surface;
a second gate structure that extends over the semiconductor fin, the second gate structure having a side surface adjacent to the first side surface of the first gate structure;
a first sidewall spacer on the first side surface of the first gate structure;
a second sidewall spacer on the side surface of the second gate structure;
a first source/drain region adjacent to the first side surface of the first gate structure, the first source/drain region including a first doped region in a first portion of the semiconductor fin and a first epitaxial semiconductor layer on the semiconductor fin over the first doped region, the first epitaxial semiconductor layer laterally positioned between the first sidewall spacer and the second sidewall spacer, the first epitaxial semiconductor layer laterally spaced from the first sidewall spacer by a first distance, and the first epitaxial semiconductor layer laterally spaced from the second sidewall spacer by a second distance; and
a second source/drain region adjacent to the second side surface of the first gate structure, the second source/drain region including a second epitaxial semiconductor layer in the cavity in the semiconductor fin.

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The structure of claim 1 wherein the semiconductor fin includes an upper section having a first side surface, a second side surface, and a top surface between the first side surface and the second side surface, and the first epitaxial semiconductor layer is arranged on the first side surface, the second side surface, and the top surface of the upper section of the semiconductor fin.

### Claim 4 (depends on 3)

The structure of claim 3 wherein the semiconductor fin includes a lower section, and the first epitaxial semiconductor layer is located over the lower section of the semiconductor fin.

### Claim 5 (depends on 4)

The structure of claim 4 further comprising:
a shallow trench isolation surrounding the lower section of the semiconductor fin, the shallow trench isolation having a top surface.

### Claim at position 6

6-13. (canceled)

### Claim 14

A method of forming a structure for a field-effect transistor, the method comprising:
forming a first gate structure that extends over a semiconductor fin, wherein the first gate structure has a first side surface and a second side surface opposite the first side surface;
forming a second gate structure that extends over the semiconductor fin, wherein the second gate structure has a side surface adjacent to the first side surface of the first gate structure;
forming a first sidewall spacer on the first side surface of the first gate structure;
forming a second sidewall spacer on the side surface of the second gate structure;
ion implanting a first portion of the semiconductor fin adjacent to the first side surface of the first gate structure with an ion implantation process to form a first doped region;
epitaxially growing a first semiconductor layer on the first portion of the semiconductor fin to provide a first source/drain region that includes the first semiconductor layer and the first doped region, wherein the first semiconductor layer is laterally positioned between the first sidewall spacer and the second sidewall spacer, the first semiconductor layer is laterally spaced from the first sidewall spacer by a first distance, and the first semiconductor layer laterally is spaced from the second sidewall spacer by a second distance; and
epitaxially growing a second semiconductor layer in a cavity in the semiconductor fin adjacent to the second side surface of the first gate structure to provide a second source/drain region.

### Claim 15

(canceled)

### Claim 16 (depends on 14)

The method of claim 14 wherein the semiconductor fin has an upper section with a first side surface, a second side surface, and a top surface connecting the first side surface and the second side surface, and the first semiconductor layer is arranged on the first side surface, the second side surface, and the top surface of the upper section of the semiconductor fin.

### Claim 17 (depends on 14)

The method of claim 14 further comprising:
forming a shallow trench isolation surrounding a lower section of the semiconductor fin,
wherein the second semiconductor layer is positioned on the lower section of the semiconductor fin.

### Claim at position 11

18-19. (canceled)

### Claim 20 (depends on 14)

The method of claim 14 wherein the first semiconductor layer is epitaxially grown in a space over the first portion of the semiconductor fin between a first sacrificial sidewall spacer and a second sacrificial sidewall spacer, and further comprising:
removing the first sacrificial sidewall spacer and the second sacrificial sidewall spacer after the first semiconductor layer is epitaxially grown.

### Claim 21 (depends on 1)

The structure of claim 1 wherein the first distance is equal to the second distance.

### Claim 22 (depends on 5)

The structure of claim 5 wherein the first epitaxial semiconductor layer is fully positioned above the top surface of the shallow trench isolation.

### Claim 23 (depends on 14)

The method of claim 14 wherein the first distance is equal to the second distance.

### Claim 24 (depends on 17)

The method of claim 17 wherein the first semiconductor layer is fully positioned above a top surface of the shallow trench isolation.

### Claim 25 (depends on 20)

The method of claim 20 further comprising:
forming a third sacrificial sidewall spacer on the second side surface of the first gate structure and a fourth sacrificial sidewall spacer on the side surface of the second gate structure; and
before epitaxially growing the second semiconductor layer, removing the third sacrificial sidewall spacer and the fourth sacrificial sidewall spacer.