# US 2021/0242343 A1 · Laterally Diffused MOSFET with Low Rsp*Qg Product

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- Number: US 2021/0242343 A1
- Document ID: US20210242343A1
- Status: Published application
- Kind: A1
- Application number: 17/302,060
- Filed: 2021-04-22
- Published: 2021-08-05
- Earliest claimed: 2018-09-13
- Assignees: Silanna Asia Pte Ltd
- Applicants: Silanna Asia Pte Ltd
- Inventors: David Snyder
- Web page: https://patentgrep.com/patent/US20210242343A1

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/657: {having substrates comprising insulating layers, e.g. SOI-LDMOS transistors}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/111: {Field plates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 84/40: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm2, a gate charge (Qg) of about 1.9-2.0 nC/mm2, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

## Claims

### Claim 1

A laterally diffused MOSFET device comprising:
a source region in an active layer;
a drain region in the active layer;
a body region in the active layer between the source region and the drain region;
a drift region in the active layer between the body region and the drain region, wherein the drift region extends to a top surface of the active layer for an entire lateral extent between the body region and the drain region without a shallow trench isolation region or a local oxidation of silicon isolation region between the body region and the drain region;
a stepped gate having a first portion disposed over the body region and a second portion disposed over a first portion of the drift region;
a first gate insulator region between the first portion of the stepped gate and the body region; and
a second gate insulator region between the second portion of the stepped gate and the first portion of the drift region.

### Claim 2 (depends on 1)

The laterally diffused MOSFET device of claim 1, wherein:
the first and second portions of the stepped gate are continuous with each other.

### Claim 3 (depends on 1)

The laterally diffused MOSFET device of claim 1, wherein:
the first gate insulator region has a first thickness; and
the second gate insulator region has a second thickness greater than the first thickness.

### Claim 4 (depends on 1)

The laterally diffused MOSFET device of claim 1, further comprising:
a gate shield, a first portion of which is disposed over a second portion of the drift region between the stepped gate and the drain region to reduce a gate-drain capacitance of the laterally diffused MOSFET device.

### Claim 5 (depends on 4)

The laterally diffused MOSFET device of claim 4, further comprising:
a shield insulator region between the first portion of the gate shield and the second portion of the drift region, the shield insulator region having a thickness of about 900-1100 Å;
wherein the gate shield laterally extends about 0.3-0.7 μm from above an edge of the stepped gate in a direction toward the drain region.

### Claim 6 (depends on 4)

The laterally diffused MOSFET device of claim 4, further comprising:
a source contact electrically connected to the source region and to the gate shield.

### Claim 7 (depends on 4)

The laterally diffused MOSFET device of claim 4, wherein:
a second portion of the gate shield is disposed over the stepped gate.

### Claim 8 (depends on 1)

The laterally diffused MOSFET device of claim 1, wherein:
the laterally diffused MOSFET device has a specific resistance (Rsp) of about 5-8 mOhm*mm2 and a gate charge (Qg) of about 1.5-3.0 nC/mm2.

### Claim 9 (depends on 1)

The laterally diffused MOSFET device of claim 1, wherein:
the laterally diffused MOSFET device has an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

### Claim 10 (depends on 1)

The laterally diffused MOSFET device of claim 1, wherein:
the first portion of the stepped gate has a first length of about 0.1-0.4 μm;
the second portion of the stepped gate has a second length of about 0.1-0.6 μm;
the first gate insulator region has a first thickness of about 30-62 Å; and
the second gate insulator region has a second thickness of about 300-500 Å.

### Claim 11 (depends on 1)

The laterally diffused MOSFET device of claim 1, wherein:
the laterally diffused MOSFET device is configured to form a channel region within the body region, a length of the channel region being about the same as a length of the first portion of the stepped gate; and
the laterally diffused MOSFET device is configured to form an accumulation region within the first portion of the drift region due to an electric field from the second portion of the stepped gate.

### Claim 12 (depends on 11)

The laterally diffused MOSFET device of claim 11, wherein:
the channel region is aligned with the first portion of the stepped gate.

### Claim 13 (depends on 1)

An electronic circuit comprising the laterally diffused MOSFET device of claim 1, the electronic circuit further comprising:
a switching element electrically connected to a phase node, the switching element comprising the laterally diffused MOSFET device;
a controller electrically connected to the laterally diffused MOSFET device to provide a drive signal to the stepped gate;
an inductor electrically connected to the phase node and an output node; and
a load electrically connected to receive an output voltage at the output node.

### Claim 14 (depends on 13)

The electronic circuit of claim 13, wherein:
the controller is operable to provide the drive signal to the stepped gate with a switching frequency of about 1-8 MHz.