# US 2021/0242342 A1 · Semiconductor device and method for manufacturing same

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- Number: US 2021/0242342 A1
- Document ID: US20210242342A1
- Status: Published application
- Kind: A1
- Application number: 17/237,343
- Filed: 2021-04-22
- Published: 2021-08-05
- Earliest claimed: 2019-01-16
- Assignees: Denso Corporation
- Applicants: Denso Corporation
- Inventors: KENTA GODA; YOUHEI ODA; YUSUKE NONAKA
- Web page: https://patentgrep.com/patent/US20210242342A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The body region is formed between the plurality of trench gate structures, and the first impurity region is formed in a surface portion of the body region. The body region includes a second conductive type contact region having an impurity concentration of the second conductive type higher than the body region and contacting the upper electrode. The first impurity region includes a first conductive type contact region having the impurity concentration of the first conductive type impurity higher than the first impurity region and contacting the upper electrode. A second conductive type contact region is formed in a part of the body region where the first impurity region is not formed without forming the first conductive type contact region therein, and a contact trench is formed in the first impurity region. The first conductive type contact region is formed in the contact trench.

## Claims

### Claim 1

A semiconductor device comprising:
a trench type semiconductor switching element having a trench gate structure, wherein:
the semiconductor switching element includes:
a drift layer having a first conductive type;
a body region having a second conductive type and arranged on the drift layer;
a first impurity region having the first conductive type, arranged in a surface portion of the body region in the body region and having an impurity concentration higher than the drift layer;
a plurality of trench gate structures, each of which includes a trench having one direction as a longitudinal direction and reaching the drift layer from the first impurity region with penetrating the body region, and a gate electrode layer disposed in the trench via an insulation film;
a high impurity concentration layer having the first or second conductive type, arranged on a side opposite to the body region with sandwiching the drift layer therebetween, and having an impurity concentration higher than the drift layer;
an upper electrode electrically connected to the first impurity region and the body region; and
a lower electrode electrically connected to the high impurity concentration layer, wherein:
the body region is disposed between the plurality of trench gate structures;
the first impurity region is disposed in a surface portion of a part of the body region;
the body region includes a second conductive type contact region having an impurity concentration of the second conductive type higher than the body region and contacting the upper electrode;
the first impurity region includes a first conductive type contact region having the impurity concentration of the first conductive type impurity higher than the first impurity region and contacting the upper electrode;
the second conductive type contact region is disposed in a part of the body region where the first impurity region is not arranged, without arranging the first conductive type contact region therein;
a contact trench is arranged in the first impurity region; and
the first conductive type contact region is disposed in the contact trench.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein:
a part of the body region where the first impurity region is not arranged, has a flat surface; and
the second conductive type contact region is arranged on the flat surface without arranging the first conductive type contact region thereon.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein:
the body region is arranged between the plurality of trench gate structures along the longitudinal direction of the trench gate structures;
the first impurity region is divided into a plurality of portions arranged in the one direction;
the surface of the body region is a planar shape between the plurality of portions of the first impurity region; and
the second conductive type contact region is arranged on the surface with the planar shape.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein:
the second conductive type contact region is arranged at a center position of the body region between the plurality of first impurity regions in an arrangement direction of the plurality of trench gate structures; and
the contact trench is arranged at a center position of the first impurity region in the arrangement direction of the plurality of trench gate structures.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein:
the body region is exposed through the contact trench; and
the second conductive type contact region is arranged on a surface of the body region exposed through the contact trench.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein:
each trench gate structure has a two-layer structure in which a shield electrode and the gate electrode layer are stacked in each of the plurality of trenches via the insulation film.

### Claim 7

A method for manufacturing a semiconductor device including a trench-type semiconductor switching element having a trench gate structure, the method comprising:
preparing a substrate having a high impurity concentration layer with a first conductive type or a second conductive type and a drift layer arranged on one surface side of the high impurity concentration layer, having the first conductive type and having an impurity concentration lower than the high impurity concentration layer;
forming a plurality of trench gate structures by forming a plurality of trenches with one direction as a longitudinal direction in the drift layer, and arranging a gate electrode layer in each of the plurality of trenches via an insulation film;
forming a body region having the second conductive type on the drift layer between the plurality of trenches;
forming a first impurity region having the first conductive type with an impurity concentration higher than the drift layer in a surface portion of a part of the body region in the body region;
forming an interlayer insulation film on the trench gate structure, the body region, and the first impurity region;
forming a contact hole connected to the body region and the first impurity region in the interlayer insulation film;
forming an upper electrode electrically connected to the first impurity region and the body region through the contact hole; and
forming a lower electrode electrically connected to the high impurity concentration layer, wherein:
the forming of the contact hole includes: forming a first contact hole connected to the first impurity region; and forming a second contact hole connected to a portion of the body region in which the first impurity region is not formed, the method further comprising:
after forming the first contact hole, ion implanting a first conductive type impurity using the interlayer insulation film as a mask to form the first conductive type contact region in the first impurity region;
forming a contact trench, exposing the first conductive type contact hole on a side surface of the contact trench, and exposing the body region on a bottom of the contact trench by etching the first impurity region including the first conductive type contact region through the first contact hole using the interlayer insulation film as a mask; and
after forming the second contact hole, ion implanting a second conductive type impurity using the interlayer insulation film as a mask to form a second conductive type contact region in the body region.