# US 2021/0242339 A1 · Transistors with an asymmetrical source and drain

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- Number: US 2021/0242339 A1
- Document ID: US20210242339A1
- Status: Published application
- Kind: A1
- Application number: 16/776,938
- Filed: 2020-01-30
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GLOBALFOUNDRIES U.S, Inc.
- Inventors: Wenjun Li; Man Gu; Baofu Zhu
- Web page: https://patentgrep.com/patent/US20210242339A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

## Claims

### Claim 1

A structure for a field-effect transistor, the structure comprising:
a semiconductor body;
a first gate structure that extends over the semiconductor body, the first gate structure including a first sidewall and a second sidewall opposite the first sidewall;
a first source/drain region including an epitaxial semiconductor layer on a first portion of the semiconductor body, the first source/drain region positioned adjacent to the first sidewall of the first gate structure; and
a second source/drain region in a second portion of the semiconductor body, the second source/drain region positioned adjacent to the second sidewall of the first gate structure,
wherein the first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

### Claim 2 (depends on 1)

The structure of claim 1 wherein the semiconductor body is a fin.

### Claim 3 (depends on 2)

The structure of claim 2 wherein the fin has a top surface, and the second source/drain region is formed in the second portion of the fin entirely below the top surface of the fin.

### Claim 4 (depends on 3)

The structure of claim 3 wherein the epitaxial semiconductor layer of the first source/drain region is formed in a cavity in the first portion of the fin, and the epitaxial semiconductor layer of the first source/drain region has a top surface that is raised above the top surface of the fin.

### Claim 5 (depends on 1)

The structure of claim 1 further comprising:
a second gate structure that extends over the semiconductor body, the second gate structure positioned adjacent to the second sidewall of the first gate structure,
wherein the second source/drain region is laterally positioned between the first gate structure and the second gate structure.

### Claim 6 (depends on 5)

The structure of claim 5 further comprising:
a third gate structure that extends over the semiconductor body, the third gate structure positioned adjacent to the first sidewall of the first gate structure,
wherein the first source/drain region is laterally positioned between the first gate structure and the third gate structure.

### Claim 7 (depends on 6)

The structure of claim 6 wherein the second gate structure has a sidewall, the third gate structure has a sidewall, the first sidewall of the first gate structure and the sidewall of the third gate structure are separated by a first distance, and the first sidewall of the first gate structure and the sidewall of the second gate structure are separated by a second distance that is greater than the first distance.

### Claim 8 (depends on 7)

The structure of claim 7 wherein the second distance is equal to an integer multiple of the first distance.

### Claim 9 (depends on 7)

The structure of claim 7 wherein the second distance is equal to two times the first distance.

### Claim 10 (depends on 1)

The structure of claim 1 wherein the second source/drain region is free of epitaxial semiconductor material.

### Claim 11 (depends on 1)

The structure of claim 1 wherein the first source/drain region includes a first concentration of a dopant, and the second source/drain region includes a second concentration of the dopant that is different from the first concentration.

### Claim 12 (depends on 1)

The structure of claim 1 wherein the first source/drain region is a source of the field-effect transistor, and the second source/drain region is a drain of the field-effect transistor.

### Claim 13

A method of forming a structure for a field-effect transistor, the method comprising:
forming a first gate structure that extends over a semiconductor body;
forming an epitaxial semiconductor layer of a first source/drain region on a first portion of the semiconductor body; and
forming a second source/drain region in a second portion of the semiconductor body,
wherein the first gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the first gate structure, the second source/drain region positioned adjacent to the second sidewall of the first gate structure, the first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

### Claim 14 (depends on 13)

The method of claim 13 wherein the semiconductor body is a fin, the fin has a top surface, and the second source/drain region is formed entirely below the top surface of the fin.

### Claim 15 (depends on 14)

The method of claim 14 wherein the epitaxial semiconductor layer of the first source/drain region is formed in a cavity in the first portion of the fin, and the epitaxial semiconductor layer of the first source/drain region has a top surface that is raised above the top surface of the fin.

### Claim 16 (depends on 13)

The method of claim 13 further comprising:
forming a second gate structure that extends over the semiconductor body,
wherein the second source/drain region is laterally positioned between the first gate structure and the second gate structure.

### Claim 17 (depends on 16)

The method of claim 16 further comprising:
forming a third gate structure that extends over the semiconductor body,
wherein the epitaxial semiconductor layer of the first source/drain region is laterally positioned between the first gate structure and the third gate structure.

### Claim 18 (depends on 17)

The method of claim 17 wherein the second gate structure has a sidewall, the third gate structure has a sidewall, the first sidewall of the first gate structure and the sidewall of the third gate structure are separated by a first distance, and the first sidewall of the first gate structure and the sidewall of the second gate structure are separated by a second distance that is greater than the first distance.

### Claim 19 (depends on 18)

The method of claim 18 wherein the second distance is equal to an integer multiple of the first distance.

### Claim 20 (depends on 13)

The method of claim 13 wherein the second source/drain region is free of epitaxial semiconductor material.