# US 2021/0242338 A1 · Process and structure for a superjunction device

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- Number: US 2021/0242338 A1
- Document ID: US20210242338A1
- Status: Published application
- Kind: A1
- Application number: 16/778,904
- Filed: 2020-01-31
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: Power Integrations, Inc.
- Applicants: Power Integrations, Inc.
- Inventors: Alexei Ankoudinov; Sorin S. Georgescu
- Web page: https://patentgrep.com/patent/US20210242338A1

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/664: {Inverted VDMOS transistors, i.e. source-down VDMOS transistors}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/154: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10P 30/202: {characterised by the semiconductor materials}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A superjunction device comprising a drain contact, a substrate layer above the drain contact, an epitaxial layer above the substrate layer, a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device, a trench with a sloped angle formed by use of a hard mask layer. The trench is filled with an insulating material. A first vertical column is formed adjacent to the trench. A second vertical column is formed adjacent to the first vertical column. A source contact is coupled to the first vertical column and the second vertical column. A P-body region is coupled to the source contact. A gate oxide is formed above the source contact and the epitaxial layer, and a gate formed above the gate oxide.

## Claims

### Claim 1

A method of forming a superjunction device structure, comprising:
depositing an epitaxial N-type layer over an N-type substrate;
depositing a hard mask layer over the epitaxial N-type layer;
etching a trench with a sloped angle on the epitaxial N-type layer;
forming a first vertical column adjacent to the trench by implantation and diffusion;
forming a second vertical column adjacent to the first vertical column by implantation and diffusion;
filling the trench with an insulating material such that a formation of key-holes is avoided;
performing a chemical-mechanical planarization (CMP) to remove the insulating material over the first and second vertical column and the epitaxial N-type layer;
depositing a gate oxide and a polysilicon layer;
etching the gate oxide and the polysilicon layer with a gate mask above the polysilicon layer to form a gate;
implanting a source contact below the gate oxide;
implanting a P-body region below the source contact;
forming a source electrode and a gate contacts; and
forming a drain contact below the N-type substrate.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
depositing a semi-insulating material into the trench to provide a near constant electric field.

### Claim 3 (depends on 1)

The method of claim 1, further comprising etching the trench to an angle between 85 to 95 degrees.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first vertical column is a P-type semiconductor and the second vertical column is an N-type semiconductor.

### Claim 5 (depends on 4)

The method of claim 4, wherein implantation doses of the first vertical column and of the second vertical column are approximately equal.

### Claim 6 (depends on 1)

The method of claim 1, further comprising implanting and diffusing boron as part of the first vertical column or the second vertical column.

### Claim 7 (depends on 1)

The method of claim 1, further comprising implanting and diffusing a phosphate as part of the first vertical column or the second vertical column.

### Claim 8 (depends on 1)

The method of claim 1, further comprising depositing a channel mask and implanting in a top portion of the p-body region to adjust a threshold voltage.

### Claim 9

A superjunction device, comprising:
a drain contact;
a substrate layer above the drain contact;
an epitaxial layer above the substrate layer;
a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device;
a trench with a sloped angle formed by use of a hard mask layer, the trench filled with an insulating material;
a first vertical column formed adjacent to the trench,
a second vertical column formed adjacent to the first vertical column;
a source contact coupled to the first vertical column and the second vertical column;
a P-body region coupled to the source contact;
a gate oxide formed above the source contact and the epitaxial layer; and
a gate formed above the gate oxide.

### Claim 10 (depends on 9)

The superjunction device of claim 9, wherein the trench extends to the substrate layer.

### Claim 11 (depends on 10)

The superjunction device of claim 10, further comprising a semi-insulating material deposited into the trench, the semi-insulating material coupled to the source contact at a top of the epitaxial layer or to the substrate layer.

### Claim 12 (depends on 11)

The superjunction device of claim 11, wherein the semi-insulating material forms a u-shape in the trench, the semi-insulating material coupled to the source contact at the top of the epitaxial layer or to the substrate layer.

### Claim 13 (depends on 11)

The superjunction device of claim 11, further comprising an epitaxial buffer layer formed between the substrate layer and a bottom of the trench.

### Claim 14 (depends on 9)

The superjunction device of claim 9, wherein the first vertical column is a P-type semiconductor and the second vertical column is an N-type semiconductor.

### Claim 15 (depends on 9)

The superjunction device of claim 9, wherein the first vertical column is an N-type semiconductor and the second vertical column is a P-type semiconductor.

### Claim 16 (depends on 9)

The superjunction device of claim 9, wherein the gate is a DMOS gate.

### Claim 17 (depends on 9)

The superjunction device of claim 9, wherein the gate is a LIMOS gate.

### Claim 18 (depends on 9)

The superjunction device of claim 9, wherein the sloped angle of the trench is between 85 to 95 degrees.

### Claim 19 (depends on 9)

The superjunction device of claim 9, further comprising: a passivation layer formed above the gate.

### Claim 20 (depends on 17)

The superjunction device of claim 17, wherein the gate is formed within the trench.

### Claim 21 (depends on 9)

The superjunction device of claim 9, wherein the trench is V-shaped to allow the trench to be filled with oxide without voids and to allow two column regions to be formed by vertical substantially zero degree implantation.