# US 2021/0242337 A1 · Barrier structure configured to increase performance of iii-v devices

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- Number: US 2021/0242337 A1
- Document ID: US20210242337A1
- Status: Published application
- Kind: A1
- Application number: 16/872,551
- Filed: 2020-05-12
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yun-Hsiang Wang; Chun Lin Tsai; Jiun-Lei Jerry Yu; Po-Chih Chen; Chia-Ling Yeh; Ching Yu Chen
- Web page: https://patentgrep.com/patent/US20210242337A1

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

## Claims

### Claim 1

An integrated chip, comprising:
an undoped layer overlying a substrate;
a first barrier layer overlying the undoped layer;
a doped layer overlying the first barrier layer; and
a second barrier layer overlying the first barrier layer, wherein the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance, wherein the first and second barrier layers comprise a same III-V semiconductor material, wherein a first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

### Claim 2 (depends on 1)

The integrated chip according to claim 1, wherein the first element is aluminum.

### Claim 3 (depends on 1)

The integrated chip according to claim 1, wherein the same III-V semiconductor material is aluminum gallium nitride.

### Claim 4 (depends on 1)

The integrated chip according to claim 1, wherein the second barrier layer is thinner than the first barrier layer.

### Claim 5 (depends on 1)

The integrated chip according to claim 1, wherein a bottom surface of the second barrier layer is disposed below a top surface of the first barrier layer by a non-zero distance.

### Claim 6 (depends on 1)

The integrated chip according to claim 1, wherein the first barrier layer has a first thickness within a middle region of the substrate, wherein the second barrier layer comprises a second thickness and is laterally offset from the middle region, wherein the first barrier layer has a third thickness within a peripheral region that is laterally offset from the middle region, and wherein the first thickness is greater than the second thickness and the third thickness.

### Claim 7 (depends on 6)

The integrated chip according to claim 6, wherein the third thickness is greater than the second thickness.

### Claim 8 (depends on 1)

The integrated chip according to claim 1, further comprising:
a gate electrode overlying the doped layer;
a first contact overlying the second barrier layer; and
a second contact overlying the second barrier layer, wherein the first and second contacts are separated from one another by the doped layer.

### Claim 9 (depends on 1)

The integrated chip according to claim 1, wherein the second atomic percentage is at least two times greater than the first atomic percentage.

### Claim 10

An integrated chip, comprising:
a buffer layer overlying a substrate;
an undoped binary III-V semiconductor layer overlying the buffer layer;
a doped binary III-V semiconductor layer overlying the undoped binary III-V semiconductor layer, wherein the doped binary III-V semiconductor layer is disposed within a middle region of the substrate; and
a barrier structure overlying the undoped binary III-V semiconductor layer, wherein the barrier structure comprises a III-V semiconductor material with a first element, wherein an atomic concentration of the first element discretely increases along a first direction that extends from the middle region to a peripheral region, where the peripheral region laterally surrounds the middle region, and wherein the first direction points away from the doped binary III-V semiconductor layer.

### Claim 11 (depends on 10)

The integrated chip according to claim 10, wherein a thickness of the barrier structure discretely increases along the first direction.

### Claim 12 (depends on 10)

The integrated chip according to claim 10, wherein the first element is aluminum.

### Claim 13 (depends on 10)

The integrated chip according to claim 10, further comprising:
a first contact overlying the barrier structure and within the peripheral region, wherein the first contact is on a first side of the doped binary III-V semiconductor layer; and
a second contact overlying the barrier structure and within the peripheral region, wherein the second contact is on a second side of the doped binary III-V semiconductor layer, wherein the first side is opposite the second side.

### Claim 14 (depends on 13)

The integrated chip according to claim 13, wherein the atomic concentration of the first element directly underlying the doped binary III-V semiconductor layer is less than the atomic concentration of the first element directly underlying the first and second contacts.

### Claim 15 (depends on 13)

The integrated chip according to claim 13, wherein a bottom surface of the first and second contacts is disposed above a bottom surface of the doped binary III-V semiconductor layer.

### Claim 16 (depends on 10)

The integrated chip according to claim 10, wherein the barrier structure comprises:
a first barrier layer disposed between the undoped binary III-V semiconductor layer and the doped binary III-V semiconductor layer, wherein the first barrier layer comprises the III-V semiconductor material; and
a second barrier layer overlying the first barrier layer, wherein the second barrier layer is laterally offset from the middle region, wherein the second barrier layer comprises the III-V semiconductor material with a higher atomic concentration of the first element relative to the first barrier layer.

### Claim 17

A method of forming an integrated chip, comprising:
depositing an undoped layer over a substrate;
depositing a first barrier layer over the undoped layer, wherein the first barrier layer comprises a III-V semiconductor material with a first atomic percentage of a first element;
forming a doped layer over the first barrier layer;
selectively forming a second barrier layer over the first barrier layer such that the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance, wherein the second barrier layer comprises the III-V semiconductor material with a second atomic percentage of the first element, wherein the second atomic percentage is greater than the first atomic percentage; and
forming a gate electrode over the doped layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein selectively forming the second barrier layer comprises:
forming a masking layer over the doped layer and the first barrier layer; and
performing a selective growth process to form the second barrier layer over the first barrier layer in regions laterally offset from the masking layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first barrier layer is deposited by an epitaxial process and the selective growth process includes performing a metal organic chemical vapor deposition (MO-CVD) process.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
forming a first contact and a second contact on the second barrier layer and laterally spaced apart from one another by the doped layer.