# US 2021/0242334 A1 · Semiconductor structure and method for forming the same

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- Number: US 2021/0242334 A1
- Document ID: US20210242334A1
- Status: Published application
- Kind: A1
- Application number: 17/152,448
- Filed: 2021-01-19
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yi-Yun LI; Tsai-Yu HUANG; Huicheng CHANG; Yee-Chia YEO
- Web page: https://patentgrep.com/patent/US20210242334A1

## CPC

- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 84/0128: {Manufacturing their channels}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/6213: {having rounded corners}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 32/1408: {from or through or into an external applied layer, e.g. photoresist or nitride layers}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate and forming an isolation structure over the substrate. In addition, the fin structure is protruded from the isolation structure. The method further includes trimming the fin structure to a first width and forming a Ge-containing material covering the fin structure. The method further includes annealing the fin structure and the Ge-containing material to form a modified fin structure. The method also includes trimming the modified fin structure to a second width.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising:
forming a fin structure over a substrate;
forming an isolation structure over the substrate, wherein the fin structure is protruded from the isolation structure;
trimming the fin structure to a first width;
forming a Ge-containing material covering the fin structure;
annealing the fin structure and the Ge-containing material to form a modified fin structure; and
trimming the modified fin structure to a second width.

### Claim 2 (depends on 1)

The method as claimed in claim 1, further comprising forming a hard mask layer covering the Ge-containing material.

### Claim 3 (depends on 2)

The method as claimed in claim 2, further comprising removing the hard mask layer after the annealing is performed.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein a Ge concentration of the modified fin structure decreases from a surface of the modified fin structure to a center of the modified fin structure after the annealing.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein when the annealing is performed, Ge diffuses from the Ge-containing material to the fin structure, and a profile of Ge in the modified fin structure extends below a top surface of the isolation structure.

### Claim 6 (depends on 1)

The method as claimed in claim 1, further comprising applying a process gas during the annealing, wherein the process gas comprises nitrogen, oxygen, ammonia, or a combination thereof.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein the first width of the fin structure is greater than the second width of the modified fin structure.

### Claim 8

A method for forming a semiconductor structure, comprising:
forming a first fin structure and a second fin structure over a substrate, wherein the second fin structure is adjacent to the first fin structure;
forming an isolation structure over the substrate, wherein the first fin structure and the second fin structure are protruded from the isolation structure;
forming a first hard mask layer covering the first fin structure;
trimming the second fin structure, wherein a first width of the first fin structure is greater than a second width of the second fin structure;
forming a Ge-containing material covering the second fin structure;
annealing the second fin structure and the Ge-containing material to form a modified second fin structure; and
trimming the modified second fin structure to a third width, wherein the first width is greater than the third width.

### Claim 9 (depends on 8)

The method as claimed in claim 8, further comprising forming a second hard mask layer covering the Ge-containing material.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein the second hard mask layer has a thickness in a range from 10 Å to 50 Å.

### Claim 11 (depends on 9)

The method as claimed in claim 9, further comprising removing the second hard mask layer after the annealing is performed.

### Claim 12 (depends on 11)

The method as claimed in claim 11, further comprising maintaining the first hard mask layer while removing the second hard mask layer.

### Claim 13 (depends on 8)

The method as claimed in claim 8, wherein the Ge-containing material has a thickness in a range from 5 Å to 30 Å prior to the annealing.

### Claim 14 (depends on 8)

The method as claimed in claim 8, wherein the Ge-containing material comprises Si1-xGex, and x is in a range from 0.15 to 0.75 prior to the annealing.

### Claim 15

A semiconductor structure, comprising:
an isolation structure formed over a substrate;
a first fin structure protruded from the isolation structure, wherein the first fin structure is doped with Ge element, and a profile of the Ge element in the first fin structure extends below a top surface of the isolation structure, wherein a doped region is formed in the first fin structure, the doped region has a tapered portion extending below the top surface of the isolation structure; and
a gate structure formed over the first fin structure.

### Claim 16 (depends on 15)

The semiconductor structure as claimed in claim 15, wherein the isolation structure has two isolation regions located on opposite sides of the first fin structure, a difference of height is formed between the top surfaces of the two isolation regions, and the doped region in the first fin structure is asymmetric.

### Claim 17 (depends on 15)

The semiconductor structure as claimed in claim 15, further comprising an anti-punch-through (APT) region located below the doped region, wherein the doped region in the first fin structure reaches the anti-punch-through region.

### Claim 18 (depends on 15)

The semiconductor structure as claimed in claim 15, wherein a Ge concentration of the first fin structure decreases from a surface of the first fin structure to a center of the first fin structure.

### Claim 19 (depends on 18)

The semiconductor structure as claimed in claim 18, wherein an undoped region is formed in the first fin structure, the undoped region has an elongated portion in the center of the first fin structure.

### Claim 20 (depends on 15)

The semiconductor structure as claimed in claim 15, further comprising a second fin structure formed over a substrate and adjacent to the first fin structure, wherein a second width of the second fin structure is greater than a first width of the first fin structure.