# US 2021/0242333 A1 · Semiconductor device and method

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- Number: US 2021/0242333 A1
- Document ID: US20210242333A1
- Status: Published application
- Kind: A1
- Application number: 16/941,445
- Filed: 2020-07-28
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wan-Yi Kao; Che-Hao Chang; Yung-Cheng Lu; Chi On Chui
- Web page: https://patentgrep.com/patent/US20210242333A1

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/097: {by thermally treating}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/17: {characterised by the semiconductor material}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a fin extending from a substrate; forming an first isolation region along opposing sidewalls of the fin; forming a gate structure over the fin; forming an epitaxial source/drain region in the fin adjacent the gate structure; forming an etch stop layer over the epitaxial source/drain region and over the gate structure; forming a protection layer over the etch stop layer, the protection layer including silicon oxynitride; and forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.

## Claims

### Claim 1

A method comprising:
forming a fin extending from a substrate;
forming an first isolation region along opposing sidewalls of the fin;
forming a gate structure over the fin;
forming an epitaxial source/drain region in the fin adjacent the gate structure;
forming an etch stop layer over the epitaxial source/drain region and over the gate structure;
forming a protection layer over the etch stop layer, the protection layer comprising silicon oxynitride; and
forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second isolation material comprises silicon oxide.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the protection layer comprises using an atomic layer deposition (ALD) process.

### Claim 4 (depends on 1)

The method of claim 1, wherein, after forming the second isolation material, the protection layer has an atomic percentage of nitrogen that is less than 10%.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the second isolation material comprises performing an anneal process that converts the protection layer from silicon oxynitride to silicon oxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein the protection layer has a thickness between 1 nm and 3 nm.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the second isolation material comprises a flowable chemical vapor deposition (FCVD) process.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming an opening extending through the second isolation material, the protection layer, and the etch stop layer to expose the epitaxial source/drain region, and depositing a conductive material within the opening.

### Claim 9

A method of forming a semiconductor device, the method comprising:
forming a semiconductor fin protruding from a substrate;
forming a gate stack over the semiconductor fin;
forming a source/drain region on the semiconductor fin adjacent the gate stack;
forming a first dielectric layer extending over the source/drain region and the gate stack;
forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is a different material than the first dielectric layer, wherein the second dielectric layer is formed having a first atomic percentage of nitrogen;
forming an insulating layer on the second dielectric layer, wherein the insulating layer is a different material than the second dielectric layer;
performing an annealing process, wherein the second dielectric layer has a second atomic percentage of nitrogen after performing the annealing process that is smaller than the first atomic percentage of nitrogen; and
after performing the annealing process, forming a conductive feature extending through the insulating layer, the second dielectric layer, and the first dielectric layer to contact the source/drain region.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first dielectric layer is silicon nitride.

### Claim 11 (depends on 9)

The method of claim 9, wherein the first dielectric layer has a thickness between 2 nm and 100 nm.

### Claim 12 (depends on 9)

The method of claim 9, wherein the annealing process is performed at a temperature between 400° C. and 1000° C.

### Claim 13 (depends on 9)

The method of claim 9, wherein the second dielectric layer is silicon oxynitride, and wherein the first atomic percentage of nitrogen is between 1% and 20%.

### Claim 14 (depends on 9)

The method of claim 9, wherein the second atomic percentage of nitrogen is less than one-fifth of the first atomic percentage of nitrogen.

### Claim 15 (depends on 9)

The method of claim 9, wherein the insulating layer is silicon oxide.

### Claim 16

A device comprising:
a fin extending from a semiconductor substrate;
a gate stack over and along a sidewall of the fin;
a gate spacer along a sidewall of the gate stack and a sidewall of the fin;
an epitaxial source/drain region in the fin and adjacent the gate stack;
a silicon nitride layer extending over the epitaxial source/drain region and the gate spacer;
a silicon oxynitride layer on the silicon nitride layer;
an insulating layer on the silicon oxynitride layer; and
a contact extending through the insulating layer, the silicon oxynitride layer, and the silicon nitride layer to the epitaxial source/drain region.

### Claim 17 (depends on 16)

The device of claim 16, wherein the insulating layer comprises silicon oxide.

### Claim 18 (depends on 16)

The device of claim 16, wherein the silicon oxynitride layer is thicker than the silicon nitride layer.

### Claim 19 (depends on 16)

The device of claim 16, wherein the silicon oxynitride layer has a thickness between 1 nm and 3 nm.

### Claim 20 (depends on 16)

The device of claim 16, wherein the silicon oxynitride layer has an atomic concentration of nitrogen that is between 1% and 20%.