# US 2021/0242329 A1 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242329 A1 - Document ID: US20210242329A1 - Status: Published application - Kind: A1 - Application number: 17/238,029 - Filed: 2021-04-22 - Published: 2021-08-05 - Earliest claimed: 2014-06-23 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: SHIN-JIUN KUANG; YI-HAN WANG; TSUNG-HSING YU; YI-MING SHEU - Web page: https://patentgrep.com/patent/US20210242329A1 ## CPC - H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel. ## Claims ### Claim 1 A semiconductor device comprising: a gate structure located on a substrate, and an interface between the gate structure and the substrate; a raised source/drain region adjacent to the gate structure, wherein the raised source/drain region comprises: a stressor layer providing strain to a channel region under the gate structure, the stressor layer including: a first silicon germanium layer at a bottom of the stressor layer; a second silicon germanium layer on the first silicon germanium layer, wherein the second silicon germanium layer includes a germanium concentration that is greater than that of the first silicon germanium layer, wherein the first and second silicon germanium layers individually includes a gradient distribution of the germanium concentration; and a silicide layer in the stressor layer, wherein the silicide layer penetrates a top surface of the raised source/drain region and extends into at least the second silicon germanium layer and ends below the interface by a predetermined depth, and the predetermined depth allows the stressor layer to maintain the strain of the channel region. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the gate structure includes a gate spacer, and the silicide layer is free from in contact with the gate spacer, and the silicide layer comprises a sheet resistance lower than that of the stressor layer. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the silicide layer is encompassed by the raised source/drain region. ### Claim 4 (depends on 1) The semiconductor device of claim 1, further comprises a contact plug located on the silicide layer, wherein a bottom area of the contact plug is substantially equal to or smaller than a top area of the silicide layer. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the raised source/drain region comprises p-type, dopants and the predetermined depth is in a range from about 0 nanometers to about 5 nanometers. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the silicide layer comprises a thickness ranging from about 11 nanometers to about 15 nanometers. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the silicide layer comprises nickel silicide, and the stressor layer comprises silicon germanium. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the stressor layer further comprises: a silicon cap layer over the second silicon germanium layer. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the first silicon germanium layer comprises a germanium concentration in a range from about 10% to about 40%, and the second silicon germanium layer comprises a germanium concentration in a range from about 25% to about 50%. ### Claim 10 A semiconductor device comprising: a gate structure located on a substrate, and an interface between the gate structure and the substrate; a raised source/drain region adjacent to the gate structure, wherein the raised source/drain region comprises an epitaxially grown material selected to exhibit a tensile or compressive stress provided to a channel region under the gate structure, the epitaxially grown material includes: a first epitaxial-grown doped layer; a second epitaxial-grown doped layer over the first epitaxial-grown doped layer, the second epitaxial-grown doped layer including a dopant concentration higher than that of the first epitaxial-grown doped layer; and a silicide plug, wherein the silicide plug penetrates a top surface of the raised source/drain region and extends into the second epitaxial-grown doped layer, and a bottommost portion of the silicide layer ends below the interface by a predetermined depth so as to enlarge a contact area coupling with the raised source/drain region, and the predetermined depth is allowed to reduce contact resistance and maintain the tensile or compressive stress of the channel region. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the gate structure includes a gate spacer, and the silicide plug is free from in contact with the gate spacer, and the silicide plug comprises a pocket profile encompassed by the raised source/drain region. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein the raised source/drain region comprises n-type dopants and the predetermined depth is in a range from about 5 nanometers to about 11 nanometers. ### Claim 13 (depends on 10) The semiconductor device of claim 10, wherein the predetermined depth is less than 7 nanometers. ### Claim 14 (depends on 10) The semiconductordevice of claim 10, wherein the raised source/drain region further comprises: a third epitaxial-grown doped layer over the second epitaxial-grown doped layer, the third epitaxial-grown doped layer including a dopant concentration higher than that of the second epitaxial-grown doped layer; and a fourth epitaxial-grown doped layer over the third epitaxial-grown doped layer, the fourth epitaxial-grown doped layer comprising a dopant concentration higher than the first, second and third epitaxial-grown doped layers. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the first, second, third and fourth epitaxial-grown doped layers individually comprise a constant distribution of a dopant concentration. ### Claim 16 A semiconductor device comprising: a gate structure located on a substrate, and an interface between the gate structure and the substrate; a raised source/drain region adjacent to the gate structure, wherein the raised source/drain region comprises: an epitaxial-grown doped layer providing a tensile or compressive stress to a channel region under the gate structure, wherein from bottom to top, the epitaxial-grown doped layer includes a first epitaxial-grown doped layer and a second epitaxial-grown doped layer; a silicon cap layer capping the epitaxial-grown doped layer; and a silicide layer, penetrating a top surface of the raised source/drain region and extending into at least the second epitaxial-grown doped layer, and the silicide layer being partially below the interface by a predetermined depth, wherein the predetermined depth allows the epitaxial-grown doped layer to maintain the strain of the channel region. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein a concentration of an epitaxially grown material in the epitaxial-grown doped layer increasingly grades from the first epitaxial-grown doped layer to the third epitaxial-grown doped layer. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the first epitaxial-grown doped layer and the second epitaxial-grown doped layer individually includes a gradient distribution of the epitaxially grown material. ### Claim 19 (depends on 16) The semiconductor device of claim 16, wherein the epitaxial-grown doped layer provides a tensile or compressive stress to a channel region in the substrate, wherein the predetermined depth allows the epitaxial-grown doped layer to maintain the strain of the channel region, and wherein the predetermined depth is in a range from about 5 nanometers to about 11 nanometers. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein an end portion of the epitaxial-grown doped layer is adjacent to the channel region.