# US 2021/0242318 A1 · Semiconductor device

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- Number: US 2021/0242318 A1
- Document ID: US20210242318A1
- Status: Published application
- Kind: A1
- Application number: 17/238,587
- Filed: 2021-04-23
- Published: 2021-08-05
- Earliest claimed: 2018-11-23
- Assignees: Denso Corporation
- Applicants: Denso Corporation
- Inventors: Mutsuya MOTOJIMA
- Web page: https://patentgrep.com/patent/US20210242318A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor layer, a source region, a drain region, a gate electrode, a first electrode, and a second electrode. The semiconductor layer has a main surface. The semiconductor layer generates a channel close to the main surface along one direction of the main surface. The source region and the drain region are disposed in a surface layer of the semiconductor layer. A portion where the channel is generated is disposed between the source region and the drain region. The gate electrode is disposed above the channel and along the one direction. The first electrode is connected to a region of the main surface corresponding to the source region. The second electrode is connected to a region of the main surface corresponding to the drain region.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor layer having a main surface and configured to generate a channel close to the main surface along one direction of the main surface;
a source region;
a drain region, wherein the source region and the drain region are disposed in a surface layer of the semiconductor layer, and a portion where the channel is generated is disposed between the source region and the drain region;
a gate electrode disposed above the channel and along the one direction;
a first electrode connected to a region of the main surface corresponding to the source region; and
a second electrode connected to a region of the main surface corresponding to the drain region, wherein
the first electrode has a plurality of first contacts connected to the region of the main surface corresponding to the source region,
the second electrode has a plurality of second contacts connected to the region of the main surface corresponding to the drain region,
the one direction is defined as a gate width direction of the gate electrode,
the plurality of first contacts are arranged in a row along the gate width direction, and
the plurality of second contacts are arranged in a row along the gate width direction.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the plurality of first contacts are arranged apart from each other, and
the plurality of second contacts are arranged apart from each other.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
another direction of the main surface perpendicular to the gate width direction is defined as a gate length direction,
the first electrode includes a first connection having a width narrower than a width of each of the plurality of first contacts in the gate length direction,
two of the plurality of first contacts adjacent to each other are connected via the first connection in the gate width direction,
the second electrode includes a second connection having a width narrower than a width of each of the plurality of second contacts in the gate length direction, and
two of the plurality of second contacts adjacent to each other are connected via the second connection in the gate width direction.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein
a number of the plurality of first contacts is two, and
a number of the plurality of second contacts is two.