# US 2021/0242316 A1 · Vertical transistor device with source/drain regions comprising a twi-dimensional (2d) material and methods of making such verticaltransistor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242316 A1 - Document ID: US20210242316A1 - Status: Published application - Kind: A1 - Application number: 16/776,711 - Filed: 2020-01-30 - Published: 2021-08-05 - Earliest claimed: 2020-01-30 - Assignees: GlobalFoundries U.S. Inc. - Applicants: GLOBALFOUNDRIES U.S. Inc. - Inventors: Heng Yang; David Pritchard; Kai Sun; Hongru Ren; Neha Nayyar; Manjunatha Prabhu; Elizabeth Strehlow; Salvatore Cimino - Web page: https://patentgrep.com/patent/US20210242316A1 ## CPC - H10D 64/252: {for vertical or pseudo-vertical devices} - H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)} - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/80: characterised by the materials - H10D 62/82: Heterojunctions - H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge - H10D 62/882: {Graphene} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure. ## Claims ### Claim 1 A vertical transistor device, comprising: a bottom source/drain region including a first plurality of layers of two-dimensional (2D) material, wherein each of the first plurality of layers of 2D material has a respective periodic crystallographic pattern with a respective rotational orientation about a first reference axis of rotation relative to each adjacent layer of the first plurality of layers of 2D material; a top source/drain region including a second plurality of layers of 2D material, wherein the top source/drain region is positioned vertically above at least a portion of the bottom source/drain region; a vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region, the vertically oriented semiconductor structure having a vertical height and an outer perimeter; and a gate structure positioned all around the outer perimeter of the vertically oriented semiconductor structure for at least a portion of the vertical height of the vertically oriented semiconductor structure. ### Claim 2 (depends on 1) The vertical transistor device of claim 1, wherein the first and second plurality of layers of 2D material each has a planar upper surface, a planar bottom surface and a substantially uniform vertical thickness, in a gate length direction of the vertical transistor device, across an entirety of the first and second plurality of layers of 2D material. ### Claim 3 (depends on 1) The vertical transistor device of claim 1, wherein a lowermost surface of the vertically oriented semiconductor structure is positioned on and in contact with the first plurality of layers of 2D material of the bottom source/drain region and an uppermost surface of the vertically oriented semiconductor structure is positioned on and in contact with the second plurality of layers of the top source/drain region. ### Claim 4 (depends on 1) The vertical transistor device of claim 1, wherein a first portion of the vertically oriented semiconductor structure positioned vertically between the gate structure and the first plurality of layers of 2D material in the bottom source/drain region comprises a dopant material and a second portion of the vertically oriented semiconductor structure positioned vertically between the gate structure and the second plurality of layers of 2D material in the top source/drain region comprises the dopant material. ### Claim 5 (canceled) ### Claim 6 (depends on 1) The vertical transistor device of claim 1, wherein each of the first and second plurality of layers of 2D material comprises a same 2D material. ### Claim 7 (depends on 1) The vertical transistor device of claim 1, wherein each of the first and second plurality of layers of 2D material have a vertical thickness that is the same. ### Claim 8 (depends on 1) The vertical transistor device of claim 1, wherein the first and second plurality of layers of 2D material in each of the bottom source/drain region and the top source/drain region comprises one of silicon, silicon germanium, a metal chalcogenide based material, a transition metal dichalcogenide (TMD), graphene, MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, HfS2, HfSe2, ZrS2, ZrSe2, NbSe2, or ReSe2. ### Claim 9 (depends on 1) The vertical transistor device of claim 1, wherein the gate structure has a vertical thickness in a gate length direction of the vertical transistor device that is less than the vertical height of the vertically oriented semiconductor structure. ### Claim 10 (canceled) ### Claim 11 (depends on 1) The vertical transistor device of claim 1, wherein the first plurality of layers of 2D material positioned in the bottom source/drain region comprise a first number of the layers of 2D material and wherein the second plurality of layers of 2D material positioned in the top source/drain region comprise a second number of the layers of 2D material, wherein the first and second numbers are different. ### Claim 12 A vertical transistor device, comprising: a bottom source/drain region comprising a first plurality of layers of two-dimensional (2D) material, wherein each of the first plurality of layers of 2D material has a respective periodic crystallographic pattern with a respective rotational orientation about a first reference axis of rotation relative to each adjacent layer of the first plurality of layers of 2D material; a top source/drain region comprising a second plurality of layers of two-dimensional (2D) material, wherein each of the second plurality of layers of 2D material has a respective periodic crystallographic pattern with a respective rotational orientation about a second reference axis of rotation relative to each adjacent layer of the second plurality of layers of 2D material and wherein, relative to a reference axis of rotation, the periodic crystallographic pattern of one of the layers of 2D material in the second plurality of layers of 2D material is rotated relative to the periodic crystallographic pattern of another of the layers of 2D material in the second plurality of layers of 2D material; a vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region, the vertically oriented semiconductor structure having a vertical height and an outer perimeter; and a gate structure positioned all around the outer perimeter of the vertically oriented semiconductor structure for at least a portion of the vertical height of the vertically oriented semiconductor structure. ### Claim 13 (canceled) ### Claim 14 (depends on 12) The vertical transistor device of claim 12, wherein a lowermost surface of the vertically oriented semiconductor structure is positioned on and in contact with an uppermost of the first plurality of layers of 2D material of the bottom source/drain region and an uppermost surface of the vertically oriented semiconductor structure is positioned on and in contact with a lowermost second plurality of layers of 2D material of the top source/drain region. ### Claim 15 (depends on 12) The vertical transistor device of claim 12, wherein a first portion of the vertically oriented semiconductor structure positioned vertically between the gate structure and the first plurality of layers of 2D material of the bottom source/drain region comprises a dopant material and a second portion of the vertically oriented semiconductor structure positioned vertically between the gate structure and the second plurality of layers of 2D material of the top source/drain region comprises the dopant material. ### Claim 16 (depends on 12) The vertical transistor device of claim 12, wherein each of the first and second plurality of layers of 2D material comprise a same 2D material. ### Claim 17 (depends on 12) The vertical transistor device of claim 12, wherein the first plurality of layers of 2D material comprises one of silicon, silicon germanium, a metal chalcogenide based material, a transition metal dichalcogenide (TMD), graphene, MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, HfS2, HfSe2, ZrS2, ZrSe2, NbSe2, or ReSe2, and wherein the second plurality of layers of 2D material comprises one of silicon, silicon germanium, a metal chalcogenide based material, a transition metal dichalcogenide (TMD), graphene, MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, HfS2, HfSe2, ZrS2, ZrSe2, NbSe2, or ReSe2. ### Claim 18 (depends on 16) The vertical transistor device of claim 16, wherein the first plurality of layers of 2D material comprise a first number of the layers of 2D material and wherein the second plurality of layers of 2D material comprise a second number of the layers of 2D material, wherein the first and second numbers are the same. ### Claim 19 A vertical transistor device, comprising: a bottom source/drain region comprising a first plurality of layers of two-dimensional (2D) material, wherein each of the first plurality of layers of 2D material has a respective periodic crystallographic pattern with a respective rotational orientation about a first reference axis of rotation relative to each adjacent layer of the first plurality of layers of 2D material; a top source/drain region comprising a second plurality of layers of two-dimensional (2D) material, wherein each of the second plurality of layers of 2D material has a respective periodic crystallographic pattern with a respective rotational orientation about a second reference axis of rotation relative to each adjacent layer of the second plurality of layers of 2D material; a vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region, the vertically oriented semiconductor structure having a vertical height and an outer perimeter, wherein a lowermost surface of the vertically oriented semiconductor structure is positioned on and in contact with an uppermost of the first plurality of layers of 2D material of the bottom source/drain region and an uppermost surface of the vertically oriented semiconductor structure is positioned on and in contact with a lowermost second plurality of layers of 2D material of the top source/drain region; and a gate structure positioned all around the outer perimeter of the vertically oriented semiconductor structure for at least a portion of the vertical height of the vertically oriented semiconductor structure. ### Claim 20 (depends on 19) The vertical transistor device of claim 19, wherein the first plurality of layers of 2D material comprise a first number of the layers of 2D material and wherein the second plurality of layers of 2D material comprise a second number of the layers of 2D material, wherein the first and second numbers are different. ### Claim 21 (depends on 1) The vertical transistor device of claim 1, wherein each of the first and second plurality of layers of 2D material have a distinct vertical thickness. ### Claim 22 (depends on 1) The vertical transistor device of claim 1, wherein each of the second plurality of layers of 2D material has a respective periodic crystallographic pattern, with a respective rotational orientation about a second reference axis of rotation. ### Claim 23 (depends on 19) The vertical transistor device of claim 19, wherein the first plurality of layers of 2D material comprises one of silicon, silicon germanium, a metal chalcogenide based material, a transition metal dichalcogenide (TMD), graphene, MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, HfS2, HfSe2, ZrS2, ZrSe2, NbSe2, or ReSe2.