# US 2021/0242312 A1 · Semiconductor transistor and fabrication method thereof

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- Number: US 2021/0242312 A1
- Document ID: US20210242312A1
- Status: Published application
- Kind: A1
- Application number: 16/831,817
- Filed: 2020-03-27
- Published: 2021-08-05
- Earliest claimed: 2020-02-04
- Assignees: United Semiconductor (Xiamen) Co., Ltd.
- Applicants: United Semiconductor (Xiamen) Co., Ltd.
- Inventors: Sheng-Hsu Liu; Shih-Hsien Huang; WEN YI TAN
- Web page: https://patentgrep.com/patent/US20210242312A1

## CPC

- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor transistor is formed on a substrate of a first conductivity type. The substrate has a main surface. An ion well of the second conductivity type is disposed in the substrate. A source region and a drain region spaced apart from the source region are disposed within the ion well. The source region and the drain region have the first conductivity type. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate and is disposed between the source region and the drain region. A gate is disposed on the epitaxial channel layer. A gate dielectric layer is disposed between gate and the epitaxial channel layer.

## Claims

### Claim 1

A semiconductor transistor, comprising:
a substrate of a first conductivity type, wherein the substrate has a main surface;
an ion well of a second conductivity type disposed in the substrate;
a source region and a drain region spaced apart from the source region disposed within the ion well, wherein the source region and the drain region have the first conductivity type;
an epitaxial channel layer of the first conductivity type grown from the main surface of the substrate and disposed between the source region and the drain region;
a gate disposed on the epitaxial channel layer; and
a gate dielectric layer disposed between gate and the epitaxial channel layer.

### Claim 2 (depends on 1)

The semiconductor transistor according to claim 1 further comprising:
a shallow trench isolation (STI) region isolating an active area (AA) region, wherein the ion well, the source region and the drain region are disposed within the AA region.

### Claim 3 (depends on 2)

The semiconductor transistor according to claim 2, wherein the STI region comprises a trench-fill layer, and wherein an upper portion of the trench-fill layer protrudes from the main surface of the substrate.

### Claim 4 (depends on 3)

The semiconductor transistor according to claim 3, wherein the epitaxial channel layer has a facet edge adjacent to the upper portion of the trench-fill layer.

### Claim 5 (depends on 4)

The semiconductor transistor according to claim 4, wherein the range of an angle between the facet edge and a sidewall of the upper portion of the trench-fill layer is between 0°˜45°.

### Claim 6 (depends on 1)

The semiconductor transistor according to claim 1, wherein the first conductivity type is P type and the second conductivity type is N type.

### Claim 7 (depends on 1)

The semiconductor transistor according to claim 1, wherein the epitaxial channel layer comprises P type doped silicon or P type doped silicon germanium.

### Claim 8 (depends on 7)

The semiconductor transistor according to claim 7, wherein the epitaxial channel layer has a P type dopant concentration range between 1E18˜1E20 atoms/cm3.

### Claim 9 (depends on 7)

The semiconductor transistor according to claim 7, wherein the P type doped silicon germanium has a germanium concentration range between 25 at. %˜50 at. %.

### Claim 10 (depends on 1)

The semiconductor transistor according to claim 1, wherein the epitaxial channel layer has a thickness range between 5 nm and 50 nm.

### Claim 11

A method for fabricating a semiconductor transistor, comprising:
providing a substrate of a first conductivity type, wherein the substrate has a main surface;
forming an ion well of a second conductivity type in the substrate;
growing an epitaxial channel layer of the first conductivity type from the main surface of the substrate;
forming a gate dielectric layer on the epitaxial channel layer;
forming a gate on the gate dielectric layer; and
forming a source region and a drain region in the substrate, wherein the source region and the drain region have the first conductivity type.

### Claim 12 (depends on 11)

The method according to claim 11 further comprising:
forming a shallow trench isolation (STI) region in the substrate, the STI region isolating an active area (AA) region, wherein the ion well, the source region and the drain region are disposed within the AA region.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the STI region comprises a trench-fill layer, and wherein an upper portion of the trench-fill layer protrudes from the main surface of the substrate.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the epitaxial channel layer has a facet edge adjacent to the upper portion of the trench-fill layer.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the range of an angle between the facet edge and a sidewall of the upper portion of the trench-fill layer is between 0°˜45°.

### Claim 16 (depends on 11)

The method according to claim 11, wherein the first conductivity type is P type and the second conductivity type is N type.

### Claim 17 (depends on 11)

The method according to claim 11, wherein the epitaxial channel layer comprises P type doped silicon or P type doped silicon germanium.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the epitaxial channel layer has a P type dopant concentration range between 1E18˜1E20 atoms/cm3.

### Claim 19 (depends on 17)

The semiconductor transistor according to claim 17, wherein the P type doped silicon germanium has a germanium concentration range between 25 at. %˜50 at. %.

### Claim 20 (depends on 11)

The method according to claim 11, wherein the epitaxial channel layer has a thickness range between 5 nm and 50 nm.