# US 2021/0242310 A1 · Method for FinFET LDD Doping

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0242310 A1
- Document ID: US20210242310A1
- Status: Published application
- Kind: A1
- Application number: 17/240,027
- Filed: 2021-04-26
- Published: 2021-08-05
- Earliest claimed: 2018-01-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun Hsiung Tsai; Ya-Yun Cheng; Shahaji B. More; Cheng-Yi Peng; Wei-Yang Lee; Kuo-Feng Yu; Yen-Ming Chen; Jian-Hao Chen
- Web page: https://patentgrep.com/patent/US20210242310A1

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/834: further characterised by the dopants
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 50/642: {Chemical etching}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 30/22: using masks
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
an isolation structure over the substrate;
a fin over the substrate and the isolation structure;
a gate structure engaging a first portion of the fin;
first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin;
source/drain (S/D) features adjacent to the first sidewall spacers; and
second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features, wherein the second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride, wherein the second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the fin includes silicon or silicon germanium.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the fin includes multiple layers of semiconductor materials.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein each of the first sidewall spacers includes multiple layers of dielectric materials, and each of second sidewall spacers includes multiple layers of dielectric materials.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first portion of the fin has a first height above a top surface of the isolation structure, the second sidewall spacers have a second height above the top surface of the isolation structure, and the second height is less than half of the first height.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first height is in a range of 40 nm to 80 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second portion of the fin includes the dopant at a concentration of 5E19 cm−2 or higher.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the second sidewall spacers include the dopant at a higher concentration than the second portion of the fin does.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the S/D features include epitaxially grown silicon, silicon carbide, or silicon germanium.

### Claim 10

A semiconductor device, comprising:
a substrate;
an isolation structure over the substrate;
a fin over the substrate and the isolation structure;
a gate structure engaging a first portion of the fin;
first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin;
source/drain (S/D) features adjacent to the first sidewall spacers; and
second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features, wherein the second sidewall spacers include a dielectric material, and the second sidewall spacers and the second portion of the fin include a same dopant, wherein the second sidewall spacers contain the dopant at a higher concentration than the second portion of the fin does, wherein the first portion of the fin has a first height above a top surface of the isolation structure, the second sidewall spacers have a second height above the top surface of the isolation structure, and the second height is less than half of the first height.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the second height is about 10 nm to about 30 nm.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the dopant includes phosphorus and the second portion of the fin includes phosphorus at a concentration of 5E19 cm−2 or higher.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein a top surface of the S/D features is above a top surface of the second portion of the fin.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein a bottom surface of the S/D features is below the top surface of the isolation structure.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein the fin includes multiple layers of semiconductor materials.

### Claim 17

A semiconductor device, comprising:
a substrate;
an isolation structure over the substrate;
a fin over the substrate and the isolation structure;
a gate structure engaging a first portion of the fin;
first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin;
source/drain (S/D) features adjacent to the first sidewall spacers; and
second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features, wherein the second sidewall spacers include silicon nitride, and the second sidewall spacers and the second portion of the fin both include phosphorus, wherein the second sidewall spacers contain phosphorus at a higher concentration than the second portion of the fin does.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the second portion of the fin includes phosphorous at a concentration of 5E19 cm−2 or higher.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the fin includes multiple layers of silicon.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein the second portion of the fin has a first height above a top surface of the isolation structure, the second sidewall spacers have a second height above the top surface of the isolation structure, the second height is less than half of the first height, and the first height is in a range from about 40 nm to about 80 nm.