# US 2021/0242309 A1 · Method of manufacturing a semiconductor device and a semiconductor device

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- Number: US 2021/0242309 A1
- Document ID: US20210242309A1
- Status: Published application
- Kind: A1
- Application number: 17/104,938
- Filed: 2020-11-25
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jui Fu HSIEH; Chih-Teng LIAO; Chih-Shan CHEN; Yi-Jen CHEN; Tzu-Chan WENG
- Web page: https://patentgrep.com/patent/US20210242309A1

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 50/267: {using plasmas}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma etching process comprises applying pulsed bias voltage and RF voltage with pulsed power.

## Claims

### Claim 1

A method of manufacturing a semiconductor device including a fin field effect transistor (Fin FET), the method comprising:
forming a fin structure over a substrate, the fin structure extending in a first direction,
forming an isolation insulating layer over the substrate so that a lower portion of the fin structure is embedded in the isolation insulating layer and an upper portion of the fin structure is exposed from the isolation insulating layer;
forming a gate structure over a part of the fin structure, the gate structure extending in a second direction crossing the first direction in plan view;
recessing, by a plasma etching process, a source/drain region of the fin structure to form a recess; and
forming an epitaxial source/drain structure over the recess in the fin structure,
wherein the plasma etching process comprises applying pulsed bias voltage and RF voltage with pulsed power.

### Claim 2 (depends on 1)

The method of claim 1, wherein, when the pulsed bias voltage is high, the pulsed power is low.

### Claim 3 (depends on 1)

The method of claim 1, wherein a duty ratio of each of the pulsed bias voltage and the pulsed power is in a range from 70% to 90%

### Claim 4 (depends on 1)

The method of claim 1, wherein the pulsed bias voltage comprises a high voltage in a range from 200 V to 400 V and a low voltage in a range from 100 V to 150 V.

### Claim 5 (depends on 1)

The method of claim 1, wherein the RF voltage comprises a high input power in a range from 1000 W to 1500 W and a low input power in a range from 300 W to 500 W.

### Claim 6 (depends on 1)

The method of claim 1, wherein the plasma etching process comprises supplying HBr gas and one or more noble gases.

### Claim 7 (depends on 6)

The method of claim 6, wherein a flow ratio of the HBr gas and the one or more noble gases is in a range from 0.3 to 0.7.

### Claim 8 (depends on 1)

The method of claim 1, wherein the plasma etching process is performed under a pressure in a range from 1 mTorr to 100 mTorr.

### Claim 9 (depends on 1)

The method of claim 1, wherein a bottom of the recess has a W-shape or a wavy shape.

### Claim 10 (depends on 1)

The method of claim 1, wherein one cycle of the pulsed bias voltage and the pulsed power having one high value time and one low value time is in a range from 0.5 sec to 20 sec.

### Claim 11

A method of manufacturing a semiconductor device including a fin field effect transistor (Fin FET), the method comprising:
forming a plurality of fin structures over a substrate, the plurality of fin structures extending in a first direction and arranged in a second direction crossing the first direction;
forming an isolation insulating layer over the substrate so that lower portions of the plurality of fin structures are embedded in the isolation insulating layer and upper portions of the plurality of fin structures are exposed from the isolation insulating layer;
recessing the source/drain regions of the plurality of fin structures to form recesses; and
forming an epitaxial source/drain structure over each of the recess of the fin structures to form a merged source/drain epitaxial layer,
wherein in the recessing the source/drain regions, a plasma etching process combining etching and deposition processes is used, and
a bottom of each of the recesses has a W-shape or a wavy shape.

### Claim 12 (depends on 11)

The method of claim 11, wherein the bottom have a W-shape having two deeper portions and one shallow portion disposed between the two deeper portions, the shallow portion having a smaller depth than the deeper portions.

### Claim 13 (depends on 12)

The method of claim 12, wherein a difference between a depth at deeper one of the deeper portions and a depth at the shallow portion is in a range from 0.5 nm to 5 nm.

### Claim 14 (depends on 11)

The method of claim 11, wherein the plasma etching process comprises applying pulsed bias voltage and RF voltage with pulsed power.

### Claim 15 (depends on 14)

The method of claim 14, wherein, when the pulsed bias voltage is high, the pulsed power is low.

### Claim 16 (depends on 15)

The method of claim 15, wherein a duty ratio of each of the pulsed bias voltage and the pulsed power is in a range from 70% to 90%.

### Claim 17 (depends on 16)

The method of claim 16, wherein at least one of the duty ratio of the pulsed bias voltage and the duty ratio of the pulsed power changes during the recessing the source/drain regions.

### Claim 18 (depends on 14)

The method of claim 14, wherein:
the pulsed bias voltage comprises a high voltage in a range from 200 V to 400 V and a low voltage in a range from 100 V to 150 V, and
the RF voltage comprises a high input power in a range from 1000 W to 1500 W and a low input power in a range from 300 W to 500 W.

### Claim 19 (depends on 14)

The method of claim 14, wherein a pulse of the pulse bias voltage is synchronous with a pulse of the RF voltage.

### Claim 20

A semiconductor device comprising:
an isolation insulating layer disposed over a substrate,
a fin structure disposed over the substrate and extending in a first direction in plan view,
a gate structure disposed over a part of the fin structure,
a source/drain epitaxial layer over a source/drain region of the fin structure; and
a dielectric layer disposed on a upper surface of the isolation insulating layer, wherein,
an interface between the source/drain epitaxial layer and the source/drain region of the fin structure has a W-shape.