# US 2021/0242308 A1 · Bipolar junction transistor with constricted collector region having high gain and early voltage product > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242308 A1 - Document ID: US20210242308A1 - Status: Published application - Kind: A1 - Application number: 16/781,674 - Filed: 2020-02-04 - Published: 2021-08-05 - Earliest claimed: 2020-02-04 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Alexei Sadovnikov; Natalia Lavrovskaya - Web page: https://patentgrep.com/patent/US20210242308A1 ## CPC - H10D 62/137: {Collector regions of BJTs} - H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)} - H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)} - H10D 62/133: {Emitter regions of BJTs} - H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs} - H10D 62/60: Impurity distributions or concentrations - H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/401: {Combinations of FETs or IGBTs with BJTs} - H10P 30/204: {into Group IV semiconductors} - H10P 30/21: {of electrically active species} - H10P 30/22: using masks - H10P 30/28: characterised by an annealing step, e.g. for activation of dopants - H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates - H10P 32/1406: {by ion implantation} - H10P 32/171: {being group IV material} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a bipolar junction transistor having a collector, a base, and an emitter. The collector includes a current collection region, a constriction region laterally adjacent to the current collection region, and a contact region laterally adjacent to the constriction region, located opposite from the current collection region. The current collection region, the constriction region laterally, and the contact region all have the same conductivity type. The base includes a current transmission region contacting the current collection region and a constricting well laterally adjacent to, and contacting, the current transmission region and contacting the constriction region. The current transmission region and the constricting well have an opposite conductivity type than the current collection region, the constriction region laterally, and the contact region. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate having a top surface; a semiconductor material in the substrate, the semiconductor material extending to the top surface; and a bipolar junction transistor, including: a collector in the semiconductor material, the collector having a first conductivity type, the collector including: a current collection region; a constriction region laterally adjacent to the current collection region; and a contact region laterally adjacent to the constriction region, located opposite from the current collection region; a base having a second conductivity type, opposite from the first conductivity type, the base including: a current transmission region; and a constricting well adjacent to, and contacting, the current transmission region and located between the constriction region and the top surface, wherein the constricting well extends deeper into the substrate from the top surface than the current transmission region; and an emitter having the first conductivity type, located over the current transmission region, opposite from the current collection region. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the current collection region and the constriction region extend to a same depth in the semiconductor material below the top surface. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the contact region and the constriction region extend to a same depth in the semiconductor material below the top surface. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein an average concentration of dopants of the first conductivity type in the current collection region is greater than an average concentration of dopants of the first conductivity type in the constriction region. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein an average concentration of dopants of the first conductivity type in the contact region is greater than an average concentration of dopants of the first conductivity type in the constriction region. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the constricting well is segmented, wherein the constricting well includes multiple segments in parallel. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the constricting well has a striated configuration, wherein the constricting well includes first constricting portions alternating with second constricting portions, the first constricting portions extending to greater depths in the semiconductor material below the top surface than the second constricting portions. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the current transmission region is located in the semiconductor material. ### Claim 10 (depends on 1) The semiconductor device of claim 1, further comprising a well, separate from the constricting well, the well having the second conductivity type, wherein an average concentration of dopants of the second conductivity type in the well is equal to an average concentration of the dopants of the second conductivity type in the constricting well. ### Claim 11 (depends on 10) The semiconductor device of claim 10, further comprising a metal oxide semiconductor (MOS) transistor in the well. ### Claim 12 A method of forming a semiconductor device, comprising: providing a substrate having a top surface, the substrate including a semiconductor material extending to the top surface; forming a collector of a bipolar junction transistor in the semiconductor material, the collector having a first conductivity type, the collector including: a current collection region; a constriction region laterally adjacent to the current collection region; and a contact region laterally adjacent to the constriction region, located opposite from the current collection region, wherein the current collection region, the constriction region, and the contact region are formed concurrently; forming a base of the bipolar junction transistor, by a process including: forming a current transmission region of the base over the current collection region, the current transmission region having a second conductivity type, opposite from the first conductivity type; and forming a constricting well of the base in the semiconductor material between the constriction region and the top surface, adjacent to, and contacting, the current transmission region, the constricting well having the second conductivity type, wherein the constricting well extends deeper into the substrate from the top surface than the current transmission region; and forming an emitter over the current transmission region, the emitter having the first conductivity type. ### Claim 13 (depends on 12) The method of claim 12, wherein forming the constricting well further includes forming a well implant mask over the top surface, the well implant mask exposing the substrate in an area for the constricting well, and implanting dopants of the second conductivity type into the semiconductor material where exposed by the well implant mask. ### Claim 14 (depends on 13) The method of claim 13, wherein the well implant mask exposes the substrate in an area for a metal oxide semiconductor (MOS) transistor, and wherein the dopants of the second conductivity type are concurrently implanted into the semiconductor material in the area for the MOS transistor. ### Claim 15 (depends on 13) The method of claim 13, wherein the well implant mask has a segmented configuration over the constriction region. ### Claim 16 (depends on 12) The method of claim 12, wherein forming the collector includes implanting dopants of the first conductivity type into the semiconductor material concurrently in the current collection region, the constriction region, and the contact region. ### Claim 17 (depends on 12) The method of claim 12, wherein forming the collector is performed so that the current collection region, the constriction region, and the contact region extend to a same depth in the semiconductor material below the top surface. ### Claim 18 (depends on 12) The method of claim 12, wherein the first conductivity type is n-type and the second conductivity type is p-type. ### Claim 19 (depends on 12) The method of claim 12, wherein forming the current transmission region includes implanting dopants of the second conductivity type into the semiconductor material in an area for the current transmission region. ### Claim 20 (depends on 12) The method of claim 12. wherein forming the current transmission region includes forming an epitaxial layer on the semiconductor material over the top surface of the substrate.