# US 2021/0242307 A1 · Performance sic diodes

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- Number: US 2021/0242307 A1
- Document ID: US20210242307A1
- Status: Published application
- Kind: A1
- Application number: 17/099,305
- Filed: 2020-11-16
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: GeneSiC Semiconductor Inc.
- Applicants: GeneSiC Semiconductor Inc.
- Inventors: Siddarth Sundaresan; Ranbir Singh; Jaehoon Park
- Web page: https://patentgrep.com/patent/US20210242307A1

## CPC

- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 8/051: {of Schottky diodes}
- H10D 8/60: Schottky-barrier diodes
- H10D 30/0515: {of vertical FETs having PN homojunction gates}
- H10D 30/662: {having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region}
- H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/328: {having PN junction gates}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/8325: {Silicon carbide}
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment relates to a semiconductor component, comprising a semiconductor body of a first conductivity type comprising a voltage blocking layer and islands of a second conductivity type on a contact surface and optionally a metal layer on the voltage blocking layer, and a first conductivity type layer comprising the first conductivity type not in contact with a gate dielectric layer or a source layer that is interspersed between the islands of the second conductivity type.

## Claims

### Claim 1

A semiconductor component, comprising a semiconductor body of a first conductivity type comprising a voltage blocking layer; and islands of a second conductivity type on a contact surface; and a first conductivity type layer comprising the first conductivity type not in contact with a gate dielectric layer or a source layer that is interspersed between the islands of the second conductivity type.

### Claim 2 (depends on 1)

The semiconductor component of claim 1, wherein the first conductivity type layer comprises a n-type layer and is formed in vertical direction such that it is completely enclosed by the voltage blocking layer comprises a n-type drift layer.

### Claim 3 (depends on 1)

The semiconductor component of claim 1, wherein doping concentration of the n-type layer is higher than that of the voltage blocking layer comprises a n-type drift layer.

### Claim 4 (depends on 1)

The semiconductor component of claim 1, wherein doping concentration of the n-type layer is in a range of 1E15 cm−3 to 1E19 cm−3.

### Claim 5 (depends on 1)

The semiconductor component of claim 1, wherein the first conductivity type layer comprises a n-type layer and is not in contact with the gate dielectric layer and the second conductivity type comprises a p-well region in a double-implanted MOSFET or a DMOSFET.

### Claim 6 (depends on 5)

The semiconductor component of claim 5, wherein a structure of the DMOSFET comprising the second conductivity type which comprises a p-well region, the gate dielectric layer, the metal layer comprises metal 1 layer on the voltage blocking layer which comprises n-drift layer further comprises a N+ substrate, gate metal layer and an interspersed N+ region and a P+ region forming a source ohmic contact region.

### Claim 7 (depends on 6)

The semiconductor component of claim 6, wherein an inter-level dielectric or an ILD layer separates the gate metal from the metal 1 layer which contacts the source ohmic contact regions.

### Claim 8 (depends on 5)

The semiconductor component of claim 5, wherein the n-type layer whose vertical extent is greater than the vertical extent of the p-well region.

### Claim 9 (depends on 5)

The semiconductor component of claim 5, wherein the n-type layer whose vertical extent is smaller than the vertical extent of the p-well region.

### Claim 10 (depends on 5)

The semiconductor component of claim 5, wherein the n-type layer whose vertical extent is greater than the vertical extent of the p-well region, but lateral extent is smaller and is non-continuous or interrupted.

### Claim 11 (depends on 1)

The semiconductor component of claim 1, wherein the first conductivity type layer comprises a n-type layer and is not in contact with the source layer comprises a N+ source layer and the second conductivity type comprises a P+ gate region in a vertical junction field effect transistor (JFET).

### Claim 12 (depends on 11)

The semiconductor component of claim 11, wherein a structure of the vertical junction field effect transistor (JFET) comprising the second conductivity type that comprises a P+ gate region, the N+ source, further comprises a N+ substrate, an interspersed source ohmic contact region and a pad metallization layer comprises a metal 1 layer.

### Claim 13 (depends on 12)

The semiconductor component of claim 12, wherein an inter-level dielectric or ILD layer separates the P+ gate region from the metal 1 layer which contacts the interspersed source ohmic contact regions.

### Claim 14 (depends on 11)

The semiconductor component of claim 11, wherein the n-type layer whose vertical extent is greater than the vertical extent of the P+ gate region.

### Claim 15 (depends on 11)

The semiconductor component of claim 11, wherein the n-type layer whose vertical extent is smaller than the vertical extent of the P+ gate region.

### Claim 16 (depends on 11)

The semiconductor component of claim 11, wherein the n-type layer whose vertical extent is greater than the vertical extent of the P+ gate region, but lateral extent is smaller and is non-continuous or interrupted.

### Claim 17

A method, comprising:
preparing a silicon carbide wafer comprising a N-drift layer formed on top of a N+ substrate; and forming an n-type layer, and
fabricating a semiconductor component,
wherein the n-type layer is formed such that it is completely buried within the N-drift layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the n-type layer is formed using epitaxial growth, followed by growing an additional n-type layer with a same doping concentration as the N-drift layer.

### Claim 19 (depends on 17)

The method of claim 17, wherein the n-type layer is formed by ion-implantation of Nitrogen or Phosphorus as a n-type implanted species.

### Claim 20 (depends on 17)

The method of claim 17, wherein an implant energy is in a range of 50 keV to 4 MeV and an implanted dose is in a range of 1E10 cm−2 to 1E14 cm−2.