# US 2021/0242304 A1 · Ferroelectric memories

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- Number: US 2021/0242304 A1
- Document ID: US20210242304A1
- Status: Published application
- Kind: A1
- Application number: 16/842,589
- Filed: 2020-04-07
- Published: 2021-08-05
- Earliest claimed: 2020-02-03
- Assignees: Industrial Technology Research Institute
- Applicants: Industrial Technology Research Institute
- Inventors: Yu-De LIN; Heng-Yuan LEE; Po-Chun YEH; Chih-Yao WANG; Hsin-Yun YANG
- Web page: https://patentgrep.com/patent/US20210242304A1

## CPC

- H10D 1/716: {having vertical extensions}
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)}
- G11C 11/22: using ferroelectric elements
- G11C 11/221: {using ferroelectric capacitors}
- H10B 53/30: characterised by the memory core region
- H10D 1/684: {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.

## Claims

### Claim 1

A ferroelectric memory, comprising:
a substrate;
a first conductive layer disposed on the substrate;
a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer;
a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer;
an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer;
a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer;
a conductive oxide layer disposed between the antiferroelectric layer; and
a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.

### Claim 2 (depends on 1)

The ferroelectric memory as claimed in claim 1, wherein the patterned oxide layer comprises silicon oxide, silicon nitride or silicon oxynitride.

### Claim 3 (depends on 1)

The ferroelectric memory as claimed in claim 1, wherein the first conductive layer, the second conductive layer and the third conductive layer comprise semiconductor, conductive dielectric or metal.

### Claim 4 (depends on 3)

The ferroelectric memory as claimed in claim 3, wherein the first conductive layer, the second conductive layer and the third conductive layer comprise zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tantalum silicide (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel silicide (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (SiNx), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), gadolinium (Gd), strontium (Sr), tungsten (W), tungsten silicide (WSi), tungsten nitride (WN), gallium (Ga) or gallium nitride (GaN).

### Claim 5 (depends on 1)

The ferroelectric memory as claimed in claim 1, wherein the antiferroelectric layer and the ferroelectric layer comprise hafnium zirconium oxide (HfZrOx), hafnium silicon oxide (HfSiOx), hafnium oxide (HfOx), hafnium yttrium oxide (HfYOx), hafnium gadolinium oxide (HfGdOx), hafnium strontium oxide (HfSrOx), strontium titanium oxide (SrTiOx), strontium calcium titanate (SrCaTiO3), Ag(Nb1-xTax)O3, barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), zirconium oxide (ZrOx) or hafnium aluminum oxide (HfAlOx).

### Claim 6 (depends on 1)

The ferroelectric memory as claimed in claim 1, wherein the conductive oxide layer comprises zinc oxide (ZnO), titanium oxide (TiOx), titanium oxynitride (TiON), tantalum oxynitride (TaON), silicon oxide (SiOx), silicon oxynitride (SiONx), ruthenium oxide (RuO), strontium ruthenium oxide (SrRuO), strontium hafnium oxide (SrHfO3), germanium oxide (GeO), tantalum oxide (TaO) or tantalum pentoxide (Ta2O5).

### Claim 7 (depends on 1)

The ferroelectric memory as claimed in claim 1, wherein the patterned oxide layer comprises a first portion and a second portion located on the first portion, wherein the second portion has more stress than that of the first portion, the first portion corresponds to the antiferroelectric layer, and the second portion corresponds to the ferroelectric layer.

### Claim 8

A ferroelectric memory, comprising:
a substrate;
a first conductive layer disposed on the substrate;
a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer;
a second conductive layer disposed on the exposed first conductive layer and
a ferroelectric layer disposed on the exposed first conductive layer and the second conductive layer;
an antiferroelectric layer disposed on the second conductive layer and located on the ferroelectric layer;
a third conductive layer disposed between the ferroelectric layer; and
a conductive oxide layer disposed on the third conductive layer and between the antiferroelectric layer.

### Claim 9 (depends on 8)

The ferroelectric memory as claimed in claim 8, wherein the patterned oxide layer comprises silicon oxide, silicon nitride or silicon oxynitride.

### Claim 10 (depends on 8)

The ferroelectric memory as claimed in claim 8, wherein the first conductive layer, the second conductive layer and the third conductive layer comprise semiconductor, conductive dielectric or metal.

### Claim 11 (depends on 10)

The ferroelectric memory as claimed in claim 10, wherein the first conductive layer, the second conductive layer and the third conductive layer comprise zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tantalum silicide (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel silicide (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (SiNx), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), gadolinium (Gd), strontium (Sr), tungsten (W), tungsten silicide (WSi), tungsten nitride (WN), gallium (Ga) or gallium nitride (GaN).

### Claim 12 (depends on 8)

The ferroelectric memory as claimed in claim 8, wherein the ferroelectric layer and the antiferroelectric layer comprise hafnium zirconium oxide (HfZrOx), hafnium silicon oxide (HfSiOx), hafnium oxide (HfOx), hafnium yttrium oxide (HfYOx), hafnium gadolinium oxide (HfGdOx), hafnium strontium oxide (HfSrOx), strontium titanium oxide (SrTiOx), strontium calcium titanate (SrCaTiO3), Ag(Nb1-xTax)O3, barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), zirconium oxide (ZrOx) or hafnium aluminum oxide (HfAlOx).

### Claim 13 (depends on 8)

The ferroelectric memory as claimed in claim 8, wherein the conductive oxide layer comprises zinc oxide (ZnO), titanium oxide (TiOx), titanium oxynitride (TiON), tantalum oxynitride (TaON), silicon oxide (SiOx), silicon oxynitride (SiONx), ruthenium oxide (RuO), strontium ruthenium oxide (SrRuO), strontium hafnium oxide (SrHfO3), germanium oxide (GeO), tantalum oxide (TaO) or tantalum pentoxide (Ta2O5).

### Claim 14 (depends on 8)

The ferroelectric memory as claimed in claim 8, wherein the patterned oxide layer comprises a first portion and a second portion located on the first portion, wherein the first portion has more stress than that of the second portion, the first portion corresponds to the ferroelectric layer, and the second portion corresponds to the antiferroelectric layer.

### Claim 15

A method for fabricating a ferroelectric memory, comprising:
providing a substrate;
forming a first conductive layer on the substrate;
forming a patterned oxide layer on the first conductive layer and the substrate, exposing a part of the first conductive layer;
forming a second conductive layer on the exposed first conductive layer and the patterned oxide layer;
forming a ferroelectric layer on the exposed first conductive layer and the second conductive layer;
forming a conductive oxide layer between the ferroelectric layer;
etching a part of the conductive oxide layer;
forming a third conductive layer on the conductive oxide layer; and
performing an annealing process, so that the ferroelectric layer surrounding the conductive oxide layer forms an antiferroelectric layer.

### Claim 16 (depends on 15)

The method for fabricating a ferroelectric memory as claimed in claim 15, wherein the step of forming the patterned oxide layer comprises forming a first sub-oxide layer, and then, forming a second sub-oxide layer on the first sub-oxide layer, and then patterning the first sub-oxide layer and the second sub-oxide layer, wherein the second sub-oxide layer has more stress than that of the first sub-oxide layer.

### Claim 17 (depends on 15)

The method for fabricating a ferroelectric memory as claimed in claim 15, wherein the annealing process has a temperature which is in a range from 350° C. to 600° C.

### Claim 18

A method for fabricating a ferroelectric memory, comprising:
providing a substrate;
forming a first conductive layer on the substrate;
forming a patterned oxide layer on the first conductive layer and the substrate, exposing a part of the first conductive layer;
forming a second conductive layer on the exposed first conductive layer and the patterned oxide layer;
forming a ferroelectric layer on the exposed first conductive layer and the second conductive layer;
forming a third conductive layer between the ferroelectric layer;
etching a part of the third conductive layer;
forming a conductive oxide layer on the third conductive layer; and
performing an annealing process, so that the ferroelectric layer surrounding the conductive oxide layer forms an antiferroelectric layer.

### Claim 19 (depends on 18)

The method for fabricating a ferroelectric memory as claimed in claim 18, wherein the step of forming the patterned oxide layer comprises forming a first sub-oxide layer, and then, forming a second sub-oxide layer on the first sub-oxide layer, and then patterning the first sub-oxide layer and the second sub-oxide layer, wherein the first sub-oxide layer has more stress than that of the second sub-oxide layer.

### Claim 20 (depends on 18)

The method for fabricating a ferroelectric memory as claimed in claim 18, wherein the annealing process has a temperature which is in a range from 350° C. to 600° C.