# US 2021/0242282 A1 · Method for fabricating memory device

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- Number: US 2021/0242282 A1
- Document ID: US20210242282A1
- Status: Published application
- Kind: A1
- Application number: 17/235,785
- Filed: 2021-04-20
- Published: 2021-08-05
- Earliest claimed: 2019-04-15
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chung-Tse Chen; Ko-Chi Chen; Tzu-Yun Chang
- Web page: https://patentgrep.com/patent/US20210242282A1

## CPC

- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.

## Claims

### Claim 1

A method for fabricating memory device, comprising:
forming a transistor on a substrate;
forming a contact structure on a source/drain region of the transistor;
forming a conductive layer on the contact structure; and
forming four memory structures on the conductive layer to form a quadrilateral structure.

### Claim 2 (depends on 1)

The method for fabricating memory device as recited in claim 1, wherein two of the four memory structures extend along a first direction as a first pair, and another two of the four memory structures extend along a second direction as a second pair, the first direction intersects the second direction.

### Claim 3 (depends on 1)

The method for fabricating memory device as recited in claim 1, further comprising:
forming four interconnection lines, respectively connected to the four memory structures.

### Claim 4 (depends on 2)

The method for fabricating memory device as recited in claim 2, further comprising:
forming a first pair of interconnection lines, respectively connected to the first pair of the four memory structures; and
forming a second pair of interconnection lines, respectively connected to the second pair of the four memory structures.

### Claim 5 (depends on 4)

The method for fabricating memory device as recited in claim 4,
wherein the first pair of interconnection lines is higher than the second pair of interconnection lines, wherein the first pair of interconnection lines has a protruding portion to contact the first pair of the four memory structures.

### Claim 6 (depends on 1)

The method for fabricating memory device as recited in claim 1, wherein each of the four memory structures is a resistive memory structure or a phase-change memory structure.

### Claim 7 (depends on 1)

The method for fabricating a memory device as recited in claim 1, wherein the conductive layer is single layer.

### Claim 8 (depends on 1)

The method for fabricating a memory device as recited in claim 1, wherein the step of forming the conductive layer comprises:
forming a metal layer on the contact structure; and
forming a via layer on the metal layer, wherein the first pair of the memory structures and the second pair of the memory structures are disposed on the via layer.

### Claim 9 (depends on 8)

The method for fabricating memory device as recited in claim 8, wherein the via layer has a concave at a central region surrounded by a peripheral region, and the four memory structures are disposed on the via layer at the peripheral region.

### Claim 10 (depends on 1)

The method for fabricating memory device as recited in claim 1, wherein the step of forming the four memory structures comprises forming a bottom electrode on the conductive layer; and forming a top electrode over the bottom electrode.

### Claim 11 (depends on 10)

The method for fabricating memory device as recited in claim 10, further comprising:
forming a first pair of interconnection lines, respectively connected to the top electrode of each of a first pair of the four memory structures; and
forming a second pair of interconnection lines, respectively connected to the top electrode of each of a second pair of the four memory structures.