# US 2021/0242280 A1 · Pretreatment method of selector device

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- Number: US 2021/0242280 A1
- Document ID: US20210242280A1
- Status: Published application
- Kind: A1
- Application number: 17/042,954
- Filed: 2019-07-12
- Published: 2021-08-05
- Earliest claimed: 2019-04-12
- Assignees: Huazhong University of Science and Technology
- Applicants: Huazhong University of Science and Technology
- Inventors: Hao TONG; Da HE; Xiangshui MIAO
- Web page: https://patentgrep.com/patent/US20210242280A1

## CPC

- H10B 63/24: {of the Ovonic threshold switching type}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/041: {Modification of switching materials after formation, e.g. doping (shaping H10N70/061)}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A pretreatment method of a selector device is provided, which includes: (1) performing a first voltage scan of a selector through selecting a voltage scan range and setting a first limit current Icc1 to obtain a resistance state R1 of a sub-threshold region thereof; (2) setting an nth limit current Icc(n) and performing an nth voltage scan of the selector according to a resistance state Rn-1 of a sub-threshold region of the selector after an n-1th voltage scan to obtain a resistance state Rn of a sub-threshold region thereof, where, Icc(n-1)<Icc(n), and an initial value of n is 2; and (3) stopping a voltage scan of the selector device under a read voltage is applied when a resistance value of a high resistance state of the selector device after the nth voltage scan is greater than a resistance value of a high resistance state of the selector device after the first voltage scan; otherwise, n=n+1, and returning to Step (2).

## Claims

### Claim 1

A pretreatment method of a selector device, the method comprising:
Step (1) of performing a first voltage scan of a selector through selecting a voltage scan range and setting a first limit current Icc1 to obtain a resistance state R1 of a sub-threshold region thereof;
Step (2) of setting an nth limit current Icc(n) and performing an nth voltage scan of the selector according to a resistance state Rn-1 of a sub-threshold region of the selector after an n−1th voltage scan to obtain a resistance state Rn of a sub-threshold region thereof,
where, Icc(n-1)<Icc(n), and an initial value of n is 2; and
Step (3) of stopping a voltage scan of the selector device under a read voltage is applied when a resistance value of a high resistance state of the selector device after the nth voltage scan is greater than a resistance value of a high resistance state of the selector device after the first voltage scan; otherwise, n=n+1, and returning to Step (2).

### Claim 2 (depends on 1)

The pretreatment method according to claim 1, wherein the read voltage is 0.5 times of a threshold voltage of the selector device after the first voltage scan.

### Claim 3 (depends on 1)

The pretreatment method according to claim 1, wherein
the first limit current Icc1 is 500 nA<Icc1<1000 uA; and
the nth limit current Icc(n) is Icc(n-1)<Icc(n)<1100 uA.

### Claim 4 (depends on 3)

The pretreatment method according to claim 3, wherein
the voltage scan range is 0 to 4 Vth; and
a manner of the voltage scan is that the voltage is progressively increased from 0 to a maximum voltage, and then scans back to 0 from the maximum voltage;
where, Vth is the threshold voltage of the selector.

### Claim 5 (depends on 4)

The pretreatment method according to claim 4, wherein the selector comprises a first electrode layer, a chalcogenide gating material layer, and a second electrode layer; and the chalcogenide gating material layer is between the first electrode layer and the second electrode layer.

### Claim 6 (depends on 5)

The pretreatment method according to claim 5, wherein a material of the chalcogenide gating material layer is at least one of SiTex, CTex, BTex, GeTex, AlTex, GeSbxTey, GeSbx, BiTex, AsTex, SnTex, and BiTex; a mixture formed from at least one compound of SiTex, CTex, BTex, GeTex, AlTex, GeSbxTey, GeSbx, BiTex, AsTex, SnTex, and BiTex doped with at least one element of N, Sb, Bi, and C; or a mixture formed from at least one compound of SiTex, CTex, BTex, GeTex, AlTex, GeSbxTey, GeSbx, BiTex, AsTex, SnTex, and BiTex doped with Si element.

### Claim 7 (depends on 4)

The pretreatment method according to claim 4, wherein both the first electrode layer and the second electrode layer are inert electrode materials, and the inert electrode materials are at least one of W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO, and IZO.

### Claim 8 (depends on 5)

The pretreatment method according to claim 5, wherein both the first electrode layer and the second electrode layer are inert electrode materials, and the inert electrode materials are at least one of W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO, and IZO.

### Claim 9 (depends on 2)

The pretreatment method according to claim 2, wherein
the first limit current Icc1 is 500 nA<Icc1<1000 uA; and
the nth limit current Icc(n) is Icc(n-1)<Icc(n)<1100 uA.

### Claim 10 (depends on 9)

The pretreatment method according to claim 9, wherein
the voltage scan range is 0 to 4 Vth; and
a manner of the voltage scan is that the voltage is progressively increased from 0 to a maximum voltage, and then scans back to 0 from the maximum voltage;
where, Vth is the threshold voltage of the selector.

### Claim 11 (depends on 10)

The pretreatment method according to claim 10, wherein the selector comprises a first electrode layer, a chalcogenide gating material layer, and a second electrode layer; and the chalcogenide gating material layer is between the first electrode layer and the second electrode layer.

### Claim 12 (depends on 11)

The pretreatment method according to claim 11, wherein a material of the chalcogenide gating material layer is at least one of SiTex, CTex, BTex, GeTex, AlTex, GeSbxTey, GeSbx, BiTex, AsTex, SnTex, and BiTex; a mixture formed from at least one compound of SiTex, CTex, BTex, GeTex, AlTex, GeSbxTey, GeSbx, BiTex, AsTex, SnTex, and BiTex doped with at least one element of N, Sb, Bi, and C; or a mixture formed from at least one compound of SiTex, CTex, BTex, GeTex, AlTex, GeSbxTey, GeSbx, BiTex, AsTex, SnTex, and BiTex doped with Si element.

### Claim 13 (depends on 10)

The pretreatment method according to claim 10, wherein both the first electrode layer and the second electrode layer are inert electrode materials, and the inert electrode materials are at least one of W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO, and IZO.

### Claim 14 (depends on 11)

The pretreatment method according to claim 11, wherein both the first electrode layer and the second electrode layer are inert electrode materials, and the inert electrode materials are at least one of W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO, and IZO.