# US 2021/0242252 A1 · Semiconductor structure, back-side illuminated image sensor and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242252 A1 - Document ID: US20210242252A1 - Status: Published application - Kind: A1 - Application number: 17/236,948 - Filed: 2021-04-21 - Published: 2021-08-05 - Earliest claimed: 2017-03-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: SHENG-CHAU CHEN; CHENG-HSIEN CHOU; MIN-FENG KAO - Web page: https://patentgrep.com/patent/US20210242252A1 ## CPC - H10F 39/199: {Back-illuminated image sensors} - H10F 39/024: {of coatings or optical elements} - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements} - H10F 39/805: {Coatings} - H10F 39/8053: {Colour filters} - H10F 39/8063: {Microlenses} - H10F 39/807: {Pixel isolation structures} - H10F 39/811: {Interconnections} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad. ## Claims ### Claim 1 A method for manufacturing a semiconductor structure, comprising: performing a first etch upon a semiconductor substrate to form a scribe line opening; performing a second etch in the scribe line opening to form a pad opening, wherein the pad opening includes an upper region and a lower region, the upper region being confined to the scribe line opening substantially from an upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower region protruding downward from the upper region, through an isolation region; and filling the pad opening with a conductive material. ### Claim 2 (depends on 1) The method of claim 1, further comprising: forming an array of pixel sensors. ### Claim 3 (depends on 2) The method of claim 2, wherein the scribe line opening extends laterally around the array of pixel sensors. ### Claim 4 (depends on 1) The method of claim 1, further comprising: depositing a buffer layer lines sidewalls of the scribe line opening. ### Claim 5 (depends on 1) The method of claim 1, wherein the isolation region extends into the semiconductor substrate. ### Claim 6 (depends on 1) The method of claim 1, further comprising: forming a passivation layer over the semiconductor substrate. ### Claim 7 (depends on 4) The method of claim 4, wherein the deposition of the buffer layer further comprises: depositing the buffer layer to line the upper surface of the semiconductor substrate and the bottom of the scribe line opening. ### Claim 8 (depends on 1) The method of claim 1, wherein a width of the upper region of the pad opening is greater than a width of the lower region of the pad opening. ### Claim 9 A method for manufacturing a semiconductor structure, comprising: performing a first etch upon a semiconductor substrate to form a scribe line opening; depositing a buffer layer lining a top surface of the semiconductor substrate and the scribe line opening; performing a second etch in the scribe line opening to etch through the semiconductor structure and the buffer layer; and filling the pad opening with a conductive material. ### Claim 10 (depends on 9) The method of claim 9, wherein the performing the second etch comprises: performing the second etch in the scribe line opening through a select region to further etch through a portion of a back end of line (BEOL) metallization stack to form a pad opening. ### Claim 11 (depends on 10) The method of claim 10, wherein a width of the select region is narrower than a width of the scribe line opening. ### Claim 12 (depends on 11) The method of claim 11, wherein the select region is centered on a center of the scribe line opening. ### Claim 13 (depends on 9) The method of claim 9, further comprising: forming a passivation layer over the semiconductor substrate. ### Claim 14 (depends on 9) The method of claim 9, wherein the deposition of the buffer layer comprises: depositing the buffer layer to line sidewalls and a bottom of the scribe line opening. ### Claim 15 (depends on 13) The method of claim 13, wherein the passivation includes silicon nitride. ### Claim 16 (depends on 9) The method of claim 9, wherein the filling the pad opening with the conductive material comprises: conformally forming a barrier layer over sidewalls and a bottom of the pad opening. ### Claim 17 (depends on 16) The method of claim 16, wherein the filling the pad opening with the conductive material further comprises: filling the pad opening with copper. ### Claim 18 A method for manufacturing a semiconductor structure, comprising: performing a first etch upon a semiconductor substrate to form a scribe line opening; forming a buffer layer over the semiconductor substrate and lining the scribe line opening; performing a second etch upon the buffer layer and an isolation region to form a pad opening; and filling the pad opening with a conductive material. ### Claim 19 (depends on 18) The method of claim 18, wherein the performing the second etch upon the buffer layer and the isolation region to form the pad opening comprises: performing the second etch upon the buffer layer, the isolation region, and a back end of line (BEOL) metallization stack to form the pad opening through a select region, the select region extending along the scribe line opening, the select region has a width narrower than that of the scribe line opening. ### Claim 20 (depends on 19) The method of claim 19, wherein the select region is centered on a center of the scribe line opening.