# US 2021/0242242 A1 · Semiconductor integrated circuit device

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- Number: US 2021/0242242 A1
- Document ID: US20210242242A1
- Status: Published application
- Kind: A1
- Application number: 17/235,603
- Filed: 2021-04-20
- Published: 2021-08-05
- Earliest claimed: 2016-07-01
- Assignees: Socionext Inc.
- Applicants: Socionext Inc.
- Inventors: Toshio HINO; Junji IWAHORI
- Web page: https://patentgrep.com/patent/US20210242242A1

## CPC

- H10D 84/907: {CMOS gate arrays}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/364: {of IGFETs}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 89/10: Integrated device layouts
- H10D 84/964: {Yield or reliability}
- H10D 84/974: {Layout specifications, i.e. inner core regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

## Claims

### Claim 1

A semiconductor integrated circuit device comprising
a circuit block having first and second cell rows each having a plurality of cells arranged in a first direction, the first and second cell rows being arranged in a second direction perpendicular to the first direction, wherein
the first cell row includes a first cell-row-terminating cell that does not contribute to a logical function of the circuit block at a first end thereof, and the second row includes a second cell-row-terminating cell that does not contribute to a logical function of the circuit block at a second end thereof, the first end of the first cell row and the second end of the second cell row being at the same position in the first direction,
a first cell is adjacent to the first cell-row-terminating cell in the first direction, and a second cell is adjacent to the second cell-row-terminating cell in the first direction,
the first and second cell-row-terminating cells each include:
a plurality of nanowires extending in the first direction;
a plurality of pads, the plurality of pads of the first cell-row-terminating cell being connected to the nanowires of the first cell-row-terminating cell, and the plurality of pads of the second cell-row-terminating cell being connected to the nanowires of the second cell-row-terminating cell; and
a plurality of gate structures extending in the second direction and including a first gate structure placed at a cell end on an inner side of the circuit block, and
the first and second cells each include:
a plurality of nanowires extending in the first direction;
a plurality of pads, the plurality of pads of the first cell being connected to the nanowires of the first cell and facing the plurality of pads of the first cell-row-terminating cell, and the plurality of pads of the second cell being connected to the nanowires of the second cell and facing the plurality of pads of the second cell-row-terminating cell,
the first and second cell-row-terminating cells have cell width different from each other, the cell width being a cell dimension in the first direction.

### Claim 2 (depends on 1)

The semiconductor integrated circuit device of claim 1, wherein
a first distance in the first direction between the plurality of pads of the first cell-row terminating cell and the plurality of pads of the first cell is the same as a second distance in the first direction between the plurality of pads of the second cell-row terminating cell and the plurality of pads of the second cell.

### Claim 3 (depends on 1)

The semiconductor integrated circuit device of claim 1, wherein
end of the plurality of pads on the inner side of the circuit block of the first and second cell-row-terminating cells do not overlap with the first gate structure in a plan view.

### Claim 4 (depends on 3)

The semiconductor integrated circuit device of claim 3, wherein
the plurality of gate structures includes a second gate structure placed at a cell end on an outer side of the circuit block.

### Claim 5

A semiconductor integrated circuit device comprising
a circuit block having first and second cell rows each having a plurality of cells arranged in a first direction, the first and second cell rows being arranged in a second direction perpendicular to the first direction, wherein
the first cell row includes a first cell-row-terminating cell that does not contribute to a logical function of the circuit block at a first end thereof, and the second row includes a second cell-row-terminating cell that does not contribute to a logical function of the circuit block at a second end thereof, the first end of the first cell row and the second end of the second cell row being at the same position in the first direction,
a first cell is adjacent to the first cell-row-terminating cell in the first direction, and a second cell is adjacent to the second cell-row-terminating cell in the first direction,
the first and second cell-row-terminating cells each include:
a plurality of nanowires extending in the first direction;
a plurality of pads, the plurality of pads of the first cell-row-terminating cell being connected to the nanowires of the first cell-row-terminating cell, and the plurality of pads of the second cell-row-terminating cell being connected to the nanowires of the second cell-row-terminating cell; and
a plurality of gate structures extending in the second direction and including a first gate structure placed at a cell end on an inner side of the circuit block, and a second gate structure adjacent to the first gate structure in the first direction, and
the first and second cells each include:
a plurality of nanowires extending in the first direction;
a plurality of pads, the plurality of pads of the first cell being connected to the nanowires of the first cell and facing the plurality of pads of the first cell-row-terminating cell, and the plurality of pads of the second cell being connected to the nanowires of the second cell and facing the plurality of pads of the second cell-row-terminating cell,
a third gate structure adjacent to the first gate structure in the first direction,
the first and second cell-row-terminating cells have cell width different from each other, the cell width being a cell dimension in the first direction,
the plurality of pads of the first and second cell-row-terminating cells are located between the first gate structure and the second gate structure,
the plurality of pads of the first and second cells are located between the first gate structure and the third gate structure.

### Claim 6 (depends on 5)

The semiconductor integrated circuit device of claim 5, wherein
a first distance in the first direction between the plurality of pads of the first cell-row terminating cell and the plurality of pads of the first cell is the same as a second distance in the first direction between the plurality of pads of the second cell-row terminating cell and the plurality of pads of the second cell.

### Claim 7 (depends on 5)

The semiconductor integrated circuit device of claim 5, wherein
end of the plurality of pads on the inner side of the circuit block of the first and second cell-row-terminating cells do not overlap with the first gate structure in a plan view.

### Claim 8 (depends on 7)

The semiconductor integrated circuit device of claim 7, wherein
the plurality of gate structures includes a fourth gate structure placed at a cell end on an outer side of the circuit block.