# US 2021/0242241 A1 · Three-dimensional nor array including vertical word lines and discrete memory elements and methods of manufacture

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- Number: US 2021/0242241 A1
- Document ID: US20210242241A1
- Status: Published application
- Kind: A1
- Application number: 17/237,447
- Filed: 2021-04-22
- Published: 2021-08-05
- Earliest claimed: 2019-12-27
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Adarsh RAJASHEKHAR; Raghuveer S. MAKALA; Rahul SHARANGPANI
- Web page: https://patentgrep.com/patent/US20210242241A1

## CPC

- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 48/362: {Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 62/80: characterised by the materials
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 62/882: {Graphene}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and a vertical stack of discrete memory material portions laterally surrounding the vertical word line.

## Claims

### Claim 1

A three-dimensional memory device, comprising:
an alternating stack of source layers and drain layers located over a substrate;
a memory opening vertically extending through the alternating stack;
a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack;
discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers; and
a vertical stack of discrete memory material portions laterally surrounding the vertical word line.

### Claim 2 (depends on 1)

The three-dimensional memory device of claim 1, wherein the memory material portions comprise ferroelectric material portions.

### Claim 3 (depends on 2)

The three-dimensional memory device of claim 2, wherein the memory material portions contact an outer sidewall of the vertical word line.

### Claim 4 (depends on 1)

The three-dimensional memory device of claim 1, wherein the memory material portions comprise charge storage material portions or floating gates.

### Claim 5 (depends on 1)

The three-dimensional memory device of claim 1, wherein each of the discrete semiconductor channels comprises a semiconductor channel layer including a cylindrical channel portion, an upper horizontally-extending portion adjoined to a top end of the cylindrical channel portion, and a lower horizontally-extending portion adjoined to a bottom end of the cylindrical channel portion.

### Claim 6 (depends on 5)

The three-dimensional memory device of claim 5, wherein each cylindrical channel portion of the semiconductor channel layers contacts an outer sidewall of a respective one of the memory material portions.

### Claim 7 (depends on 5)

The three-dimensional memory device of claim 5, further comprising semiconductor oxide spacers laterally surrounding and contacting the vertical word line, wherein each of the semiconductor oxide spacers contacts one the memory material portions, one of the insulating layers, and at least one of the source layers and the drain layers.

### Claim 8 (depends on 7)

The three-dimensional memory device of claim 7, wherein each of the semiconductor oxide spacers comprises:
a vertically-extending segment laterally surrounding the vertical word line; and
a laterally-extending portion adjoined a top end or a bottom end of the vertically-extending segment and comprising an annular horizontal surface that contacts a respective one of the memory material portions.

### Claim 9 (depends on 7)

The three-dimensional memory device of claim 7, wherein each of the memory material portions comprises:
an inner cylindrical sidewall contacting the vertical word line;
an outer cylindrical sidewall contacting a respective cylindrical channel portion of the semiconductor channel layers;
an upper annular surface contacting a bottom surface of an overlying one of the semiconductor oxide spacers; and
a lower annular surface contacting a top surface of an underlying one of the semiconductor oxide spacers.

### Claim 10 (depends on 5)

The three-dimensional memory device of claim 5, further comprising a channel-level insulating layer laterally surrounding the cylindrical channel portion and located between the upper horizontally-extending portion and the lower horizontally extending portion of the semiconductor channel layer, and encapsulating an airgap.

### Claim 11 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the source layer comprises a vertical stack of a doped semiconductor source layer and a metallic source layer; and
the drain layer comprises a vertical stack of a doped semiconductor drain layer and a metallic drain layer.

### Claim 12 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
each source layer consists of a metallic source layer; and
each drain layer consists of a metallic drain layer.

### Claim 13 (depends on 1)

The three-dimensional memory device of claim 1, wherein the discrete semiconductor channels comprise indium gallium zinc oxide, germanium, silicon germanium, or a two-dimensional semiconductor material layer.

### Claim 14

A method of forming a three-dimensional memory device, comprising:
forming a vertical repetition of unit layer stacks over a substrate, wherein each of the unit layer stacks comprises a source-level material layer, a sacrificial channel-level spacer layer, a drain-level material layer, and an inter-transistor-level insulating layer, wherein the source-level material layers are formed as, or are subsequently replaced with, source layers comprising at least one source-side conductive material, and the drain-level material layers are formed as, or are subsequently replaced with, drain layers comprising at least one drain-side conductive material;
forming memory openings vertically extending through the vertical repetition;
forming a vertical stack of annular recess cavities around each of the memory openings by laterally recessing the sacrificial channel-level spacer layers relative to the source-level material layers, the drain-level material layers, and the inter-transistor-level insulating layers;
forming at least one semiconductor oxide spacer over the source-level material layers and the drain-level material layers;
forming a vertical stack of memory material portions in the vertical stacks of annular recess cavities;
forming a vertical word line in each of the memory openings;
forming a backside trench through the vertical repetition; and
replacing each of the sacrificial channel-level spacer layers with a respective semiconductor channel layer through the backside trench.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the memory material portions comprise ferroelectric material portions; and
each of the vertical word lines is formed on a respective vertical stack of ferroelectric material portions among the ferroelectric material portions.

### Claim 16 (depends on 14)

The method of claim 14, wherein:
each of the source-level material layers comprises a respective sacrificial source-level material layer;
each of the drain-level material layers comprises a respective sacrificial drain-level material layer; and
the method further comprises replacing the sacrificial source-level material layers with metallic source layers and replacing the sacrificial drain-level material layers with metallic drain layers through the backside trench.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
each of the source-level material layers further comprises a respective doped semiconductor source layer;
each of the drain-level material layers further comprises a respective doped semiconductor drain layer; and
each of the semiconductor channel layers is formed directly on a respective doped semiconductor source layer and a respective doped semiconductor drain layer.

### Claim 18 (depends on 14)

The method of claim 14, wherein:
each of the source-level material layers comprises a metallic source layer;
each of the drain-level material layers comprises a metallic drain layer; and
each of the semiconductor channel layers is formed directly on a respective metallic source layer and a respective metallic drain layer.

### Claim 19 (depends on 14)

The method of claim 14, wherein:
each of the source-level material layers and the drain-level material layers comprises a semiconductor material or silicon nitride;
the at least one semiconductor oxide spacer comprises a plurality of semiconductor oxide spacers that are formed by oxidizing surface portions of the source-level material layers and the drain-level material layers into semiconductor oxide portions.

### Claim 20 (depends on 14)

The method of claim 14, wherein:
the at least one semiconductor oxide spacer is formed as a continuous semiconductor oxide spacer vertically extending through the vertical repetition; and
the method further comprises removing portions of the continuous semiconductor oxide spacer at each level of the memory material portions after removal of the sacrificial channel-level spacers,
wherein remaining portions of the continuous semiconductor oxide spacer comprise a vertical stack of semiconductor oxide spacers that are vertically spaced apart at the levels of the memory material portions.